From d79780a480a54ca039a1fd51ba420b2cc36c105d Mon Sep 17 00:00:00 2001
From: PurplePower <60787289+PurplePower@users.noreply.github.com>
Date: Wed, 27 Dec 2023 14:01:29 +0800
Subject: [PATCH] Fixed vivado script import path error

---
 lab1/vivado/z710/riscv-z710-v2020.tcl | 4 ++--
 lab2/vivado/z710/riscv-z710-v2020.tcl | 4 ++--
 lab3/vivado/z710/riscv-z710-v2020.tcl | 4 ++--
 lab4/vivado/z710/riscv-z710-v2020.tcl | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/lab1/vivado/z710/riscv-z710-v2020.tcl b/lab1/vivado/z710/riscv-z710-v2020.tcl
index 0034547..dd04bb5 100644
--- a/lab1/vivado/z710/riscv-z710-v2020.tcl
+++ b/lab1/vivado/z710/riscv-z710-v2020.tcl
@@ -190,10 +190,10 @@ set obj [get_filesets utils_1]
 
 # Adding sources referenced in BDs, if not already added
 if { [get_files Top.v] == "" } {
-  import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
 }
 if { [get_files clock_control.v] == "" } {
-  import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
 }
 
 
diff --git a/lab2/vivado/z710/riscv-z710-v2020.tcl b/lab2/vivado/z710/riscv-z710-v2020.tcl
index 0034547..dd04bb5 100644
--- a/lab2/vivado/z710/riscv-z710-v2020.tcl
+++ b/lab2/vivado/z710/riscv-z710-v2020.tcl
@@ -190,10 +190,10 @@ set obj [get_filesets utils_1]
 
 # Adding sources referenced in BDs, if not already added
 if { [get_files Top.v] == "" } {
-  import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
 }
 if { [get_files clock_control.v] == "" } {
-  import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
 }
 
 
diff --git a/lab3/vivado/z710/riscv-z710-v2020.tcl b/lab3/vivado/z710/riscv-z710-v2020.tcl
index 0034547..dd04bb5 100644
--- a/lab3/vivado/z710/riscv-z710-v2020.tcl
+++ b/lab3/vivado/z710/riscv-z710-v2020.tcl
@@ -190,10 +190,10 @@ set obj [get_filesets utils_1]
 
 # Adding sources referenced in BDs, if not already added
 if { [get_files Top.v] == "" } {
-  import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
 }
 if { [get_files clock_control.v] == "" } {
-  import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
 }
 
 
diff --git a/lab4/vivado/z710/riscv-z710-v2020.tcl b/lab4/vivado/z710/riscv-z710-v2020.tcl
index 0034547..dd04bb5 100644
--- a/lab4/vivado/z710/riscv-z710-v2020.tcl
+++ b/lab4/vivado/z710/riscv-z710-v2020.tcl
@@ -190,10 +190,10 @@ set obj [get_filesets utils_1]
 
 # Adding sources referenced in BDs, if not already added
 if { [get_files Top.v] == "" } {
-  import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
 }
 if { [get_files clock_control.v] == "" } {
-  import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
 }