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fixes for lab3, passed verilator sim and all tests with correct cf prints

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PurplePower
2025-08-15 00:57:34 +08:00
parent 47c801d5d7
commit bd3a38a3c1
2 changed files with 2 additions and 2 deletions
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2
docs/docs/better-tut/labs/lab3/lab3-pipelined-cpu.md
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@@ -115,7 +115,7 @@
我们在 `src/main/scala/riscv/core/fivestage_stall/InstructionDecode.scala` 中留下了相应接口，请根据上述约定使 ID 输出合适的寄存器地址，以供后续冒险分析。完成后应能通过 `DecoderStallTest` 测试。 我们在 `src/main/scala/riscv/core/fivestage_stall/InstructionDecode.scala` 中留下了相应接口，请根据上述约定使 ID 输出合适的寄存器地址，以供后续冒险分析。完成后应能通过 `DecoderStallTest` 测试。
我们用一个控制单元来检测并解决控制冒险和数据冒险，模块接口已经定义在 `src/main/scala/riscv/core/fivestage_stall/Control.scala`，请根据以上分析，修改 `// Lab3(Stall)` 处的代码，使其能够通过 `FiveStageCPUStallTest` 测试。 我们用一个控制单元来检测并解决控制冒险和数据冒险，模块接口已经定义在 `src/main/scala/riscv/core/fivestage_stall/Control.scala`，请根据以上分析，修改 `// Lab3(ThreeStage)` 处的代码，使其能够通过 `FiveStageCPUStallTest` 测试。

2
lab3/verilog/verilator/sim_main.cpp
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@@ -205,7 +205,7 @@ class Simulator {
top->eval(); top->eval();
top->io_interrupt_flag = 0; top->io_interrupt_flag = 0;
if (top->io_deviceSelect == 2 && top->io_memory_bundle_write_enable) { if (top->io_device_select == 2 && top->io_memory_bundle_write_enable) {
if (uart_write_time_counter == 0) std::cout << (char)top->io_memory_bundle_write_data << std::flush; // Output to UART if (uart_write_time_counter == 0) std::cout << (char)top->io_memory_bundle_write_data << std::flush; // Output to UART
uart_write_time_counter = (uart_write_time_counter + 1) % uart_write_time_limit; uart_write_time_counter = (uart_write_time_counter + 1) % uart_write_time_limit;
} }