From bd3a38a3c12f4f4629bb7e28aa6d233d49945571 Mon Sep 17 00:00:00 2001
From: PurplePower <60787289+PurplePower@users.noreply.github.com>
Date: Fri, 15 Aug 2025 00:57:34 +0800
Subject: [PATCH] fixes for lab3, passed verilator sim and all tests with
 correct cf prints

---
 docs/docs/better-tut/labs/lab3/lab3-pipelined-cpu.md | 2 +-
 lab3/verilog/verilator/sim_main.cpp                  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/docs/better-tut/labs/lab3/lab3-pipelined-cpu.md b/docs/docs/better-tut/labs/lab3/lab3-pipelined-cpu.md
index 0e3a9c3..71e57f7 100644
--- a/docs/docs/better-tut/labs/lab3/lab3-pipelined-cpu.md
+++ b/docs/docs/better-tut/labs/lab3/lab3-pipelined-cpu.md
@@ -115,7 +115,7 @@
 
     我们在 `src/main/scala/riscv/core/fivestage_stall/InstructionDecode.scala` 中留下了相应接口，请根据上述约定使 ID 输出合适的寄存器地址，以供后续冒险分析。完成后应能通过 `DecoderStallTest` 测试。
 
-    我们用一个控制单元来检测并解决控制冒险和数据冒险，模块接口已经定义在 `src/main/scala/riscv/core/fivestage_stall/Control.scala`，请根据以上分析，修改 `// Lab3(Stall)` 处的代码，使其能够通过 `FiveStageCPUStallTest` 测试。
+    我们用一个控制单元来检测并解决控制冒险和数据冒险，模块接口已经定义在 `src/main/scala/riscv/core/fivestage_stall/Control.scala`，请根据以上分析，修改 `// Lab3(ThreeStage)` 处的代码，使其能够通过 `FiveStageCPUStallTest` 测试。
 
 
 
diff --git a/lab3/verilog/verilator/sim_main.cpp b/lab3/verilog/verilator/sim_main.cpp
index ffeea56..1404ad1 100644
--- a/lab3/verilog/verilator/sim_main.cpp
+++ b/lab3/verilog/verilator/sim_main.cpp
@@ -205,7 +205,7 @@ class Simulator {
       top->eval();
       top->io_interrupt_flag = 0;
 
-      if (top->io_deviceSelect == 2 && top->io_memory_bundle_write_enable) {
+      if (top->io_device_select == 2 && top->io_memory_bundle_write_enable) {
         if (uart_write_time_counter == 0) std::cout << (char)top->io_memory_bundle_write_data << std::flush;  // Output to UART
         uart_write_time_counter = (uart_write_time_counter + 1) % uart_write_time_limit;
       }