Lab3 pipelined CPU renewed

- added tutorial
- fix ID reg addr invalid in certain types of instructions
- renamed some variables for better understanding

lab1/src/main/scala/board/verilator/Top.scala

@@ -24,20 +24,20 @@ class Top extends Module {
   val io = IO(new CPUBundle)
 
   val cpu = Module(new CPU)
-
-  io.deviceSelect := 0.U
   cpu.io.debug_read_address := io.debug_read_address
   io.debug_read_data := cpu.io.debug_read_data
 
+  // intercept UART signals
+  io.deviceSelect := cpu.io.deviceSelect
+
+  // CPU instruction input is controlled by external codes
   io.memory_bundle <> cpu.io.memory_bundle
   io.instruction_address := cpu.io.instruction_address
   cpu.io.instruction := io.instruction
-
   cpu.io.instruction_valid := io.instruction_valid
-
 }
 
 object VerilogGenerator extends App {
   (new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/verilator"), Seq(ChiselGeneratorAnnotation(() =>
     new Top())))
-}
+}