mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
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b9865cd612
- added tutorial - fix ID reg addr invalid in certain types of instructions - renamed some variables for better understanding
44 lines
1.4 KiB
Scala
44 lines
1.4 KiB
Scala
// Copyright 2022 Canbin Huang
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package board.verilator
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import chisel3._
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import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
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import peripheral._
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import riscv.{CPUBundle, Parameters}
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import riscv.core.CPU
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class Top extends Module {
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val io = IO(new CPUBundle)
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val cpu = Module(new CPU)
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cpu.io.debug_read_address := io.debug_read_address
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io.debug_read_data := cpu.io.debug_read_data
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// intercept UART signals
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io.deviceSelect := cpu.io.deviceSelect
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// CPU instruction input is controlled by external codes
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io.memory_bundle <> cpu.io.memory_bundle
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io.instruction_address := cpu.io.instruction_address
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cpu.io.instruction := io.instruction
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cpu.io.instruction_valid := io.instruction_valid
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}
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object VerilogGenerator extends App {
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(new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/verilator"), Seq(ChiselGeneratorAnnotation(() =>
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new Top())))
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}
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