实验一的取指&译码

.idea/.gitignore

@@ -0,0 +1,8 @@
+# 默认忽略的文件
+/shelf/
+/workspace.xml
+# 基于编辑器的 HTTP 客户端请求
+/httpRequests/
+# Datasource local storage ignored files
+/dataSources/
+/dataSources.local.xml

.idea/2025-fall-yatcpu-repo.iml

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<module type="JAVA_MODULE" version="4">
+  <component name="NewModuleRootManager" inherit-compiler-output="true">
+    <exclude-output />
+    <content url="file://$MODULE_DIR$" />
+    <orderEntry type="inheritedJdk" />
+    <orderEntry type="sourceFolder" forTests="false" />
+  </component>
+</module>

.idea/codeStyles/codeStyleConfig.xml

@@ -0,0 +1,5 @@
+<component name="ProjectCodeStyleConfiguration">
+  <state>
+    <option name="PREFERRED_PROJECT_CODE_STYLE" value="Default" />
+  </state>
+</component>

.idea/misc.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="ProjectRootManager" version="2" languageLevel="JDK_17" project-jdk-name="temurin-17" project-jdk-type="JavaSDK">
+    <output url="file://$PROJECT_DIR$/out" />
+  </component>
+</project>

.idea/modules.xml

@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="ProjectModuleManager">
+    <modules>
+      <module fileurl="file://$PROJECT_DIR$/.idea/2025-fall-yatcpu-repo.iml" filepath="$PROJECT_DIR$/.idea/2025-fall-yatcpu-repo.iml" />
+    </modules>
+  </component>
+</project>

.idea/vcs.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="VcsDirectoryMappings">
+    <mapping directory="" vcs="Git" />
+  </component>
+</project>

lab1/src/main/scala/riscv/core/Execute.scala

@@ -52,8 +52,6 @@ class Execute extends Module {
 
 
 
-
-
   // lab1(Execute) end
 
   io.mem_alu_result := alu.io.result

lab1/src/main/scala/riscv/core/InstructionDecode.scala

@@ -178,13 +178,25 @@ class InstructionDecode extends Module {
   )
 
   // lab1(InstructionDecode)
-
-
-
-
-
-
-
+  io.ex_aluop2_source := Mux(opcode === InstructionTypes.RM,
+    ALUOp2Source.Register,
+    ALUOp2Source.Immediate
+  )
+  // 仅当指令是 Load 类型时，才使能内存读。
+  io.memory_read_enable := opcode === InstructionTypes.L
+  // 仅当指令是 Store 类型时，才使能内存写。
+  io.memory_write_enable := opcode === InstructionTypes.S
+  // 根据指令类型，选择写回寄存器的数据来源。
+  io.wb_reg_write_source := MuxLookup(
+    opcode,
+    RegWriteSource.ALUResult // 默认来源是ALU计算结果
+  )( // 使用新的 MuxLookup 语法
+    IndexedSeq(
+      InstructionTypes.L -> RegWriteSource.Memory,           // Load 指令来源是内存
+      Instructions.jal     -> RegWriteSource.NextInstructionAddress, // jal/jalr 来源是下一条指令地址 (PC+4)
+      Instructions.jalr    -> RegWriteSource.NextInstructionAddress
+    )
+  )
   // lab1(InstructionDecode) end
   io.reg_write_enable := (opcode === InstructionTypes.RM) || (opcode === InstructionTypes.I) ||
     (opcode === InstructionTypes.L) || (opcode === Instructions.auipc) || (opcode === Instructions.lui) ||

lab1/src/main/scala/riscv/core/InstructionFetch.scala

@@ -37,6 +37,12 @@ class InstructionFetch extends Module {
     io.instruction := io.instruction_read_data
     // lab1(InstructionFetch)
 
+    when(io.jump_flag_id) {
+      pc := io.jump_address_id
+    }.otherwise {
+      pc := pc + 4.U
+    }
+
 
 
     // la1(InstructionFetch) end