diff --git a/.idea/.gitignore b/.idea/.gitignore
new file mode 100644
index 0000000..a7cdac7
--- /dev/null
+++ b/.idea/.gitignore
@@ -0,0 +1,8 @@
+# 默认忽略的文件
+/shelf/
+/workspace.xml
+# 基于编辑器的 HTTP 客户端请求
+/httpRequests/
+# Datasource local storage ignored files
+/dataSources/
+/dataSources.local.xml
diff --git a/.idea/2025-fall-yatcpu-repo.iml b/.idea/2025-fall-yatcpu-repo.iml
new file mode 100644
index 0000000..18ec59d
--- /dev/null
+++ b/.idea/2025-fall-yatcpu-repo.iml
@@ -0,0 +1,9 @@
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/codeStyles/codeStyleConfig.xml b/.idea/codeStyles/codeStyleConfig.xml
new file mode 100644
index 0000000..df5f35d
--- /dev/null
+++ b/.idea/codeStyles/codeStyleConfig.xml
@@ -0,0 +1,5 @@
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/misc.xml b/.idea/misc.xml
new file mode 100644
index 0000000..fbd542f
--- /dev/null
+++ b/.idea/misc.xml
@@ -0,0 +1,6 @@
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/modules.xml b/.idea/modules.xml
new file mode 100644
index 0000000..069e9e1
--- /dev/null
+++ b/.idea/modules.xml
@@ -0,0 +1,8 @@
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/vcs.xml b/.idea/vcs.xml
new file mode 100644
index 0000000..c8397c9
--- /dev/null
+++ b/.idea/vcs.xml
@@ -0,0 +1,6 @@
+
+
+
+
+
+
\ No newline at end of file
diff --git a/lab1/src/main/scala/riscv/core/Execute.scala b/lab1/src/main/scala/riscv/core/Execute.scala
index d51dc46..c2b16a0 100644
--- a/lab1/src/main/scala/riscv/core/Execute.scala
+++ b/lab1/src/main/scala/riscv/core/Execute.scala
@@ -52,8 +52,6 @@ class Execute extends Module {
-
-
// lab1(Execute) end
io.mem_alu_result := alu.io.result
diff --git a/lab1/src/main/scala/riscv/core/InstructionDecode.scala b/lab1/src/main/scala/riscv/core/InstructionDecode.scala
index 14868a7..6226602 100644
--- a/lab1/src/main/scala/riscv/core/InstructionDecode.scala
+++ b/lab1/src/main/scala/riscv/core/InstructionDecode.scala
@@ -178,13 +178,25 @@ class InstructionDecode extends Module {
)
// lab1(InstructionDecode)
-
-
-
-
-
-
-
+ io.ex_aluop2_source := Mux(opcode === InstructionTypes.RM,
+ ALUOp2Source.Register,
+ ALUOp2Source.Immediate
+ )
+ // 仅当指令是 Load 类型时，才使能内存读。
+ io.memory_read_enable := opcode === InstructionTypes.L
+ // 仅当指令是 Store 类型时，才使能内存写。
+ io.memory_write_enable := opcode === InstructionTypes.S
+ // 根据指令类型，选择写回寄存器的数据来源。
+ io.wb_reg_write_source := MuxLookup(
+ opcode,
+ RegWriteSource.ALUResult // 默认来源是ALU计算结果
+ )( // 使用新的 MuxLookup 语法
+ IndexedSeq(
+ InstructionTypes.L -> RegWriteSource.Memory, // Load 指令来源是内存
+ Instructions.jal -> RegWriteSource.NextInstructionAddress, // jal/jalr 来源是下一条指令地址 (PC+4)
+ Instructions.jalr -> RegWriteSource.NextInstructionAddress
+ )
+ )
// lab1(InstructionDecode) end
io.reg_write_enable := (opcode === InstructionTypes.RM) || (opcode === InstructionTypes.I) ||
(opcode === InstructionTypes.L) || (opcode === Instructions.auipc) || (opcode === Instructions.lui) ||
diff --git a/lab1/src/main/scala/riscv/core/InstructionFetch.scala b/lab1/src/main/scala/riscv/core/InstructionFetch.scala
index 67ae55c..e6b5bfa 100644
--- a/lab1/src/main/scala/riscv/core/InstructionFetch.scala
+++ b/lab1/src/main/scala/riscv/core/InstructionFetch.scala
@@ -37,6 +37,12 @@ class InstructionFetch extends Module {
io.instruction := io.instruction_read_data
// lab1(InstructionFetch)
+ when(io.jump_flag_id) {
+ pc := io.jump_address_id
+ }.otherwise {
+ pc := pc + 4.U
+ }
+
// la1(InstructionFetch) end