mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
synced 2026-02-20 20:10:14 +00:00
update z7-10 project scripts for other labs
This commit is contained in:
PurplePower
@@ -3,7 +3,7 @@
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#
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# riscv-z710-v2020.tcl: Tcl script for re-creating project 'riscv-z710-v2020'
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#
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# Generated by Vivado on Mon Dec 25 11:27:52 +0800 2023
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# Generated by Vivado on Mon Nov 18 22:07:05 +0800 2024
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# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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@@ -23,14 +23,13 @@
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# 2. The following source(s) files that were local or imported into the original project.
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# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
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#
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# <none>
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# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710/riscv-z710-v2020/riscv-z710-v2020.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v"
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#
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# 3. The following remote source files that were added to the original project:-
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#
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# "E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v"
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# "E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v"
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# "E:/Workplace/2022-fall-yatcpu-repo/lab1/vivado/z710/pre-generate-files/v2020/design_1/hdl/design_1_wrapper.v"
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# "E:/Workplace/2022-fall-yatcpu-repo/lab1/vivado/z710/z710.xdc"
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# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710/Top.v"
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# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710/clock_control.v"
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# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710/z710.xdc"
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#
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#*****************************************************************************************
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@@ -131,9 +130,14 @@ set files [list \
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[file normalize "${origin_dir}/../../verilog/z710/Top.v"] \
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[file normalize "${origin_dir}/../../verilog/z710/clock_control.v"] \
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]
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# [file normalize "${origin_dir}/pre-generate-files/v2020/design_1/hdl/design_1_wrapper.v"] \
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add_files -norecurse -fileset $obj $files
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# Import local files from the original project
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# set files [list \
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# [file normalize "${origin_dir}/riscv-z710-v2020/riscv-z710-v2020.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" ]\
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# ]
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# set imported_files [import_files -fileset sources_1 $files]
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# Set 'sources_1' fileset file properties for remote files
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# None
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@@ -177,6 +181,7 @@ set obj [get_filesets sim_1]
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set obj [get_filesets sim_1]
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set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
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set_property -name "top" -value "Top" -objects $obj
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set_property -name "top_auto_set" -value "0" -objects $obj
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set_property -name "top_file" -value "../../verilog/z710/Top.v" -objects $obj
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set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
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@@ -190,10 +195,10 @@ set obj [get_filesets utils_1]
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# Adding sources referenced in BDs, if not already added
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if { [get_files Top.v] == "" } {
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import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
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import_files -quiet -fileset sources_1 ../../verilog/z710/Top.v
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}
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if { [get_files clock_control.v] == "" } {
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import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
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import_files -quiet -fileset sources_1 ../../verilog/z710/clock_control.v
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}
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@@ -307,7 +312,7 @@ proc cr_bd_design_1 { parentCell } {
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# Create ports
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set enable_clk [ create_bd_port -dir I -type data enable_clk ]
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set io_alive_led [ create_bd_port -dir O io_alive_led ]
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set io_clock [ create_bd_port -dir I -type clk -freq_hz 50000000 io_clock ]
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set io_clock [ create_bd_port -dir I -type clk -freq_hz 125000000 io_clock ]
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set io_reset [ create_bd_port -dir I -type rst io_reset ]
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# Create instance: Top_0, and set properties
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@@ -405,7 +410,7 @@ proc cr_bd_design_1 { parentCell } {
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CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
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CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
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CONFIG.PCW_ENET1_RESET_ENABLE {0} \
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CONFIG.PCW_ENET_RESET_ENABLE {1} \
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CONFIG.PCW_ENET_RESET_ENABLE {0} \
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CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
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CONFIG.PCW_ENET_RESET_SELECT {<Select>} \
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CONFIG.PCW_EN_4K_TIMER {0} \
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@@ -467,55 +472,55 @@ proc cr_bd_design_1 { parentCell } {
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CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_15_PULLUP {enabled} \
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CONFIG.PCW_MIO_15_SLEW {slow} \
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CONFIG.PCW_MIO_16_DIRECTION {out} \
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CONFIG.PCW_MIO_16_DIRECTION {inout} \
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CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_16_PULLUP {enabled} \
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CONFIG.PCW_MIO_16_SLEW {fast} \
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CONFIG.PCW_MIO_17_DIRECTION {out} \
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CONFIG.PCW_MIO_17_DIRECTION {inout} \
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CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_17_PULLUP {enabled} \
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CONFIG.PCW_MIO_17_SLEW {fast} \
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CONFIG.PCW_MIO_18_DIRECTION {out} \
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CONFIG.PCW_MIO_18_DIRECTION {inout} \
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CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_18_PULLUP {enabled} \
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CONFIG.PCW_MIO_18_SLEW {fast} \
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CONFIG.PCW_MIO_19_DIRECTION {out} \
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CONFIG.PCW_MIO_19_DIRECTION {inout} \
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CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_19_PULLUP {enabled} \
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CONFIG.PCW_MIO_19_SLEW {fast} \
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CONFIG.PCW_MIO_1_DIRECTION {out} \
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CONFIG.PCW_MIO_1_DIRECTION {inout} \
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CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_1_PULLUP {enabled} \
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CONFIG.PCW_MIO_1_SLEW {slow} \
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CONFIG.PCW_MIO_20_DIRECTION {out} \
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CONFIG.PCW_MIO_20_DIRECTION {inout} \
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CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_20_PULLUP {enabled} \
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CONFIG.PCW_MIO_20_SLEW {fast} \
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CONFIG.PCW_MIO_21_DIRECTION {out} \
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CONFIG.PCW_MIO_21_DIRECTION {inout} \
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CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_21_PULLUP {enabled} \
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CONFIG.PCW_MIO_21_SLEW {fast} \
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CONFIG.PCW_MIO_22_DIRECTION {in} \
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CONFIG.PCW_MIO_22_DIRECTION {inout} \
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CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_22_PULLUP {enabled} \
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CONFIG.PCW_MIO_22_SLEW {fast} \
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CONFIG.PCW_MIO_23_DIRECTION {in} \
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CONFIG.PCW_MIO_23_DIRECTION {inout} \
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CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_23_PULLUP {enabled} \
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CONFIG.PCW_MIO_23_SLEW {fast} \
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CONFIG.PCW_MIO_24_DIRECTION {in} \
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CONFIG.PCW_MIO_24_DIRECTION {inout} \
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CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_24_PULLUP {enabled} \
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CONFIG.PCW_MIO_24_SLEW {fast} \
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CONFIG.PCW_MIO_25_DIRECTION {in} \
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CONFIG.PCW_MIO_25_DIRECTION {inout} \
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CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_25_PULLUP {enabled} \
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CONFIG.PCW_MIO_25_SLEW {fast} \
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CONFIG.PCW_MIO_26_DIRECTION {in} \
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CONFIG.PCW_MIO_26_DIRECTION {inout} \
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CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_26_PULLUP {enabled} \
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CONFIG.PCW_MIO_26_SLEW {fast} \
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CONFIG.PCW_MIO_27_DIRECTION {in} \
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CONFIG.PCW_MIO_27_DIRECTION {inout} \
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CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_27_PULLUP {enabled} \
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CONFIG.PCW_MIO_27_SLEW {fast} \
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@@ -599,7 +604,7 @@ proc cr_bd_design_1 { parentCell } {
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CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_45_PULLUP {enabled} \
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CONFIG.PCW_MIO_45_SLEW {slow} \
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CONFIG.PCW_MIO_46_DIRECTION {out} \
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CONFIG.PCW_MIO_46_DIRECTION {inout} \
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CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_46_PULLUP {enabled} \
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CONFIG.PCW_MIO_46_SLEW {slow} \
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@@ -639,7 +644,7 @@ proc cr_bd_design_1 { parentCell } {
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CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_5_PULLUP {disabled} \
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CONFIG.PCW_MIO_5_SLEW {slow} \
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CONFIG.PCW_MIO_6_DIRECTION {out} \
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CONFIG.PCW_MIO_6_DIRECTION {inout} \
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CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_6_PULLUP {disabled} \
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CONFIG.PCW_MIO_6_SLEW {slow} \
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@@ -798,8 +803,8 @@ proc cr_bd_design_1 { parentCell } {
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CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
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CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
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CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
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CONFIG.PCW_USB0_RESET_ENABLE {1} \
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CONFIG.PCW_USB0_RESET_IO {MIO 46} \
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CONFIG.PCW_USB0_RESET_ENABLE {0} \
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CONFIG.PCW_USB0_RESET_IO {<Select>} \
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CONFIG.PCW_USB0_USB0_IO {<Select>} \
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CONFIG.PCW_USB1_RESET_ENABLE {0} \
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CONFIG.PCW_USB_RESET_ENABLE {1} \
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@@ -820,9 +825,9 @@ proc cr_bd_design_1 { parentCell } {
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# Create port connections
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connect_bd_net -net Top_0_io_led [get_bd_ports io_alive_led] [get_bd_pins Top_0/io_led]
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connect_bd_net -net Top_0_io_tx [get_bd_pins Top_0/io_tx] [get_bd_pins processing_system7_0/UART0_RX]
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connect_bd_net -net clock_control_0_clk_out [get_bd_pins Top_0/clock] [get_bd_pins clock_control_0/clk_out]
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connect_bd_net -net clock_control_0_clk_out [get_bd_pins Top_0/clock] [get_bd_pins clock_control_0/clock_out]
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connect_bd_net -net enable_clk_1 [get_bd_ports enable_clk] [get_bd_pins clock_control_0/enable_clk]
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connect_bd_net -net io_clock_1 [get_bd_ports io_clock] [get_bd_pins clock_control_0/clk_in]
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connect_bd_net -net io_clock_1 [get_bd_ports io_clock] [get_bd_pins clock_control_0/clock_in]
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connect_bd_net -net io_reset_1 [get_bd_ports io_reset] [get_bd_pins Top_0/reset]
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connect_bd_net -net xlconstant_0_dout [get_bd_pins Top_0/io_rx] [get_bd_pins xlconstant_0/dout]
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@@ -831,32 +836,32 @@ proc cr_bd_design_1 { parentCell } {
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# Perform GUI Layout
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regenerate_bd_layout -layout_string {
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"ActiveEmotionalView":"Default View",
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"Default View_ScaleFactor":"1.39048",
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"Default View_TopLeft":"-268,0",
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"Default View_ScaleFactor":"1.0",
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"Default View_TopLeft":"-329,-33",
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"ExpandedHierarchyInLayout":"",
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"guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:9.0 non-TLS
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# -string -flagsOSRD
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preplace port DDR -pg 1 -lvl 3 -x 560 -y 60 -defaultsOSRD
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preplace port FIXED_IO -pg 1 -lvl 3 -x 560 -y 80 -defaultsOSRD
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preplace port io_alive_led -pg 1 -lvl 3 -x 560 -y 310 -defaultsOSRD
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preplace port io_reset -pg 1 -lvl 0 -x 0 -y 300 -defaultsOSRD
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preplace port io_clock -pg 1 -lvl 0 -x 0 -y 220 -defaultsOSRD
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preplace port enable_clk -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
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preplace inst Top_0 -pg 1 -lvl 2 -x 390 -y 300 -defaultsOSRD
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preplace inst clock_control_0 -pg 1 -lvl 1 -x 130 -y 230 -defaultsOSRD
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preplace port DDR -pg 1 -lvl 3 -x 570 -y 60 -defaultsOSRD
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preplace port FIXED_IO -pg 1 -lvl 3 -x 570 -y 80 -defaultsOSRD
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preplace port enable_clk -pg 1 -lvl 0 -x -10 -y 240 -defaultsOSRD
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preplace port io_alive_led -pg 1 -lvl 3 -x 570 -y 310 -defaultsOSRD
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preplace port io_clock -pg 1 -lvl 0 -x -10 -y 220 -defaultsOSRD
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preplace port io_reset -pg 1 -lvl 0 -x -10 -y 300 -defaultsOSRD
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preplace inst processing_system7_0 -pg 1 -lvl 2 -x 400 -y 120 -defaultsOSRD
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preplace inst xlconstant_0 -pg 1 -lvl 1 -x 130 -y 360 -defaultsOSRD
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preplace inst processing_system7_0 -pg 1 -lvl 2 -x 390 -y 120 -defaultsOSRD
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preplace netloc xlconstant_0_dout 1 1 1 240J 320n
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preplace netloc clock_control_0_clk_out 1 1 1 240 230n
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preplace netloc Top_0_io_tx 1 2 1 540 140n
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preplace inst Top_0 -pg 1 -lvl 2 -x 400 -y 300 -defaultsOSRD
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preplace inst clock_control_0 -pg 1 -lvl 1 -x 130 -y 230 -defaultsOSRD
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preplace netloc Top_0_io_led 1 2 1 NJ 310
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preplace netloc io_reset_1 1 0 2 NJ 300 NJ
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preplace netloc io_clock_1 1 0 1 NJ 220
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preplace netloc Top_0_io_tx 1 2 1 550 130n
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preplace netloc clock_control_0_clk_out 1 1 1 250 230n
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preplace netloc enable_clk_1 1 0 1 NJ 240
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preplace netloc processing_system7_0_DDR 1 2 1 NJ 60
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preplace netloc processing_system7_0_FIXED_IO 1 2 1 NJ 80
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levelinfo -pg 1 0 130 390 560
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pagesize -pg 1 -db -bbox -sgen -120 0 690 420
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preplace netloc io_clock_1 1 0 1 NJ 220
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preplace netloc io_reset_1 1 0 2 NJ 300 NJ
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preplace netloc xlconstant_0_dout 1 1 1 250J 320n
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preplace netloc processing_system7_0_FIXED_IO 1 2 1 550J 80n
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preplace netloc processing_system7_0_DDR 1 2 1 550J 60n
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levelinfo -pg 1 -10 130 400 570
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pagesize -pg 1 -db -bbox -sgen -130 0 700 420
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"
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}
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@@ -872,11 +877,10 @@ cr_bd_design_1 ""
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set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ]
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set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ]
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# call make_wrapper to create wrapper files
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# make wrapper for design_1.db
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set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
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add_files -norecurse -fileset sources_1 $wrapper_path
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# Create 'synth_1' run (if not found)
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if {[string equal [get_runs -quiet synth_1] ""]} {
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create_run -name synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
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Reference in New Issue
Block a user