From a64186bddbd75bccb2fb7bd03e954a4930551f48 Mon Sep 17 00:00:00 2001 From: PurplePower <60787289+PurplePower@users.noreply.github.com> Date: Tue, 19 Nov 2024 00:44:37 +0800 Subject: [PATCH] update z7-10 project scripts for other labs --- lab2/vivado/z710/riscv-z710-v2020.tcl | 108 +++++++++++++------------- lab3/vivado/z710/riscv-z710-v2020.tcl | 108 +++++++++++++------------- lab4/vivado/z710/riscv-z710-v2020.tcl | 108 +++++++++++++------------- 3 files changed, 168 insertions(+), 156 deletions(-) diff --git a/lab2/vivado/z710/riscv-z710-v2020.tcl b/lab2/vivado/z710/riscv-z710-v2020.tcl index dd04bb5..a68fb4e 100644 --- a/lab2/vivado/z710/riscv-z710-v2020.tcl +++ b/lab2/vivado/z710/riscv-z710-v2020.tcl @@ -3,7 +3,7 @@ # # riscv-z710-v2020.tcl: Tcl script for re-creating project 'riscv-z710-v2020' # -# Generated by Vivado on Mon Dec 25 11:27:52 +0800 2023 +# Generated by Vivado on Mon Nov 18 22:07:05 +0800 2024 # IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -23,14 +23,13 @@ # 2. The following source(s) files that were local or imported into the original project. # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) # -# +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710/riscv-z710-v2020/riscv-z710-v2020.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" # # 3. The following remote source files that were added to the original project:- # -# "E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v" -# "E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v" -# "E:/Workplace/2022-fall-yatcpu-repo/lab1/vivado/z710/pre-generate-files/v2020/design_1/hdl/design_1_wrapper.v" -# "E:/Workplace/2022-fall-yatcpu-repo/lab1/vivado/z710/z710.xdc" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710/Top.v" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710/clock_control.v" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710/z710.xdc" # #***************************************************************************************** @@ -131,9 +130,14 @@ set files [list \ [file normalize "${origin_dir}/../../verilog/z710/Top.v"] \ [file normalize "${origin_dir}/../../verilog/z710/clock_control.v"] \ ] -# [file normalize "${origin_dir}/pre-generate-files/v2020/design_1/hdl/design_1_wrapper.v"] \ add_files -norecurse -fileset $obj $files +# Import local files from the original project +# set files [list \ +# [file normalize "${origin_dir}/riscv-z710-v2020/riscv-z710-v2020.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" ]\ +# ] +# set imported_files [import_files -fileset sources_1 $files] + # Set 'sources_1' fileset file properties for remote files # None @@ -177,6 +181,7 @@ set obj [get_filesets sim_1] set obj [get_filesets sim_1] set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj set_property -name "top" -value "Top" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "top_file" -value "../../verilog/z710/Top.v" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj @@ -190,10 +195,10 @@ set obj [get_filesets utils_1] # Adding sources referenced in BDs, if not already added if { [get_files Top.v] == "" } { - import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v" + import_files -quiet -fileset sources_1 ../../verilog/z710/Top.v } if { [get_files clock_control.v] == "" } { - import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v" + import_files -quiet -fileset sources_1 ../../verilog/z710/clock_control.v } @@ -307,7 +312,7 @@ proc cr_bd_design_1 { parentCell } { # Create ports set enable_clk [ create_bd_port -dir I -type data enable_clk ] set io_alive_led [ create_bd_port -dir O io_alive_led ] - set io_clock [ create_bd_port -dir I -type clk -freq_hz 50000000 io_clock ] + set io_clock [ create_bd_port -dir I -type clk -freq_hz 125000000 io_clock ] set io_reset [ create_bd_port -dir I -type rst io_reset ] # Create instance: Top_0, and set properties @@ -405,7 +410,7 @@ proc cr_bd_design_1 { parentCell } { CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ CONFIG.PCW_ENET1_RESET_ENABLE {0} \ - CONFIG.PCW_ENET_RESET_ENABLE {1} \ + CONFIG.PCW_ENET_RESET_ENABLE {0} \ CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ CONFIG.PCW_ENET_RESET_SELECT {} \ CONFIG.PCW_USB0_USB0_IO {} \ CONFIG.PCW_EN_4K_TIMER {0} \ @@ -467,55 +472,55 @@ proc cr_bd_design_1 { parentCell } { CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ CONFIG.PCW_MIO_15_PULLUP {enabled} \ CONFIG.PCW_MIO_15_SLEW {slow} \ - CONFIG.PCW_MIO_16_DIRECTION {out} \ + CONFIG.PCW_MIO_16_DIRECTION {inout} \ CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_16_PULLUP {enabled} \ CONFIG.PCW_MIO_16_SLEW {fast} \ - CONFIG.PCW_MIO_17_DIRECTION {out} \ + CONFIG.PCW_MIO_17_DIRECTION {inout} \ CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_17_PULLUP {enabled} \ CONFIG.PCW_MIO_17_SLEW {fast} \ - CONFIG.PCW_MIO_18_DIRECTION {out} \ + CONFIG.PCW_MIO_18_DIRECTION {inout} \ CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_18_PULLUP {enabled} \ CONFIG.PCW_MIO_18_SLEW {fast} \ - CONFIG.PCW_MIO_19_DIRECTION {out} \ + CONFIG.PCW_MIO_19_DIRECTION {inout} \ CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_19_PULLUP {enabled} \ CONFIG.PCW_MIO_19_SLEW {fast} \ - CONFIG.PCW_MIO_1_DIRECTION {out} \ + CONFIG.PCW_MIO_1_DIRECTION {inout} \ CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ CONFIG.PCW_MIO_1_PULLUP {enabled} \ CONFIG.PCW_MIO_1_SLEW {slow} \ - CONFIG.PCW_MIO_20_DIRECTION {out} \ + CONFIG.PCW_MIO_20_DIRECTION {inout} \ CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_20_PULLUP {enabled} \ CONFIG.PCW_MIO_20_SLEW {fast} \ - CONFIG.PCW_MIO_21_DIRECTION {out} \ + CONFIG.PCW_MIO_21_DIRECTION {inout} \ CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_21_PULLUP {enabled} \ CONFIG.PCW_MIO_21_SLEW {fast} \ - CONFIG.PCW_MIO_22_DIRECTION {in} \ + CONFIG.PCW_MIO_22_DIRECTION {inout} \ CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_22_PULLUP {enabled} \ CONFIG.PCW_MIO_22_SLEW {fast} \ - CONFIG.PCW_MIO_23_DIRECTION {in} \ + CONFIG.PCW_MIO_23_DIRECTION {inout} \ CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_23_PULLUP {enabled} \ CONFIG.PCW_MIO_23_SLEW {fast} \ - CONFIG.PCW_MIO_24_DIRECTION {in} \ + CONFIG.PCW_MIO_24_DIRECTION {inout} \ CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_24_PULLUP {enabled} \ CONFIG.PCW_MIO_24_SLEW {fast} \ - CONFIG.PCW_MIO_25_DIRECTION {in} \ + CONFIG.PCW_MIO_25_DIRECTION {inout} \ CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_25_PULLUP {enabled} \ CONFIG.PCW_MIO_25_SLEW {fast} \ - CONFIG.PCW_MIO_26_DIRECTION {in} \ + CONFIG.PCW_MIO_26_DIRECTION {inout} \ CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_26_PULLUP {enabled} \ CONFIG.PCW_MIO_26_SLEW {fast} \ - CONFIG.PCW_MIO_27_DIRECTION {in} \ + CONFIG.PCW_MIO_27_DIRECTION {inout} \ CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_27_PULLUP {enabled} \ CONFIG.PCW_MIO_27_SLEW {fast} \ @@ -599,7 +604,7 @@ proc cr_bd_design_1 { parentCell } { CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_45_PULLUP {enabled} \ CONFIG.PCW_MIO_45_SLEW {slow} \ - CONFIG.PCW_MIO_46_DIRECTION {out} \ + CONFIG.PCW_MIO_46_DIRECTION {inout} \ CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ CONFIG.PCW_MIO_46_PULLUP {enabled} \ CONFIG.PCW_MIO_46_SLEW {slow} \ @@ -639,7 +644,7 @@ proc cr_bd_design_1 { parentCell } { CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ CONFIG.PCW_MIO_5_PULLUP {disabled} \ CONFIG.PCW_MIO_5_SLEW {slow} \ - CONFIG.PCW_MIO_6_DIRECTION {out} \ + CONFIG.PCW_MIO_6_DIRECTION {inout} \ CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ CONFIG.PCW_MIO_6_PULLUP {disabled} \ CONFIG.PCW_MIO_6_SLEW {slow} \ @@ -798,8 +803,8 @@ proc cr_bd_design_1 { parentCell } { CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \ CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ - CONFIG.PCW_USB0_RESET_ENABLE {1} \ - CONFIG.PCW_USB0_RESET_IO {MIO 46} \ + CONFIG.PCW_USB0_RESET_ENABLE {0} \ + CONFIG.PCW_USB0_RESET_IO {} \ CONFIG.PCW_USB1_RESET_ENABLE {0} \ CONFIG.PCW_USB_RESET_ENABLE {1} \ @@ -820,9 +825,9 @@ proc cr_bd_design_1 { parentCell } { # Create port connections connect_bd_net -net Top_0_io_led [get_bd_ports io_alive_led] [get_bd_pins Top_0/io_led] connect_bd_net -net Top_0_io_tx [get_bd_pins Top_0/io_tx] [get_bd_pins processing_system7_0/UART0_RX] - connect_bd_net -net clock_control_0_clk_out [get_bd_pins Top_0/clock] [get_bd_pins clock_control_0/clk_out] + connect_bd_net -net clock_control_0_clk_out [get_bd_pins Top_0/clock] [get_bd_pins clock_control_0/clock_out] connect_bd_net -net enable_clk_1 [get_bd_ports enable_clk] [get_bd_pins clock_control_0/enable_clk] - connect_bd_net -net io_clock_1 [get_bd_ports io_clock] [get_bd_pins clock_control_0/clk_in] + connect_bd_net -net io_clock_1 [get_bd_ports io_clock] [get_bd_pins clock_control_0/clock_in] connect_bd_net -net io_reset_1 [get_bd_ports io_reset] [get_bd_pins Top_0/reset] connect_bd_net -net xlconstant_0_dout [get_bd_pins Top_0/io_rx] [get_bd_pins xlconstant_0/dout] @@ -831,32 +836,32 @@ proc cr_bd_design_1 { parentCell } { # Perform GUI Layout regenerate_bd_layout -layout_string { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"1.39048", - "Default View_TopLeft":"-268,0", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-329,-33", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:9.0 non-TLS # -string -flagsOSRD -preplace port DDR -pg 1 -lvl 3 -x 560 -y 60 -defaultsOSRD -preplace port FIXED_IO -pg 1 -lvl 3 -x 560 -y 80 -defaultsOSRD -preplace port io_alive_led -pg 1 -lvl 3 -x 560 -y 310 -defaultsOSRD -preplace port io_reset -pg 1 -lvl 0 -x 0 -y 300 -defaultsOSRD -preplace port io_clock -pg 1 -lvl 0 -x 0 -y 220 -defaultsOSRD -preplace port enable_clk -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD -preplace inst Top_0 -pg 1 -lvl 2 -x 390 -y 300 -defaultsOSRD -preplace inst clock_control_0 -pg 1 -lvl 1 -x 130 -y 230 -defaultsOSRD +preplace port DDR -pg 1 -lvl 3 -x 570 -y 60 -defaultsOSRD +preplace port FIXED_IO -pg 1 -lvl 3 -x 570 -y 80 -defaultsOSRD +preplace port enable_clk -pg 1 -lvl 0 -x -10 -y 240 -defaultsOSRD +preplace port io_alive_led -pg 1 -lvl 3 -x 570 -y 310 -defaultsOSRD +preplace port io_clock -pg 1 -lvl 0 -x -10 -y 220 -defaultsOSRD +preplace port io_reset -pg 1 -lvl 0 -x -10 -y 300 -defaultsOSRD +preplace inst processing_system7_0 -pg 1 -lvl 2 -x 400 -y 120 -defaultsOSRD preplace inst xlconstant_0 -pg 1 -lvl 1 -x 130 -y 360 -defaultsOSRD -preplace inst processing_system7_0 -pg 1 -lvl 2 -x 390 -y 120 -defaultsOSRD -preplace netloc xlconstant_0_dout 1 1 1 240J 320n -preplace netloc clock_control_0_clk_out 1 1 1 240 230n -preplace netloc Top_0_io_tx 1 2 1 540 140n +preplace inst Top_0 -pg 1 -lvl 2 -x 400 -y 300 -defaultsOSRD +preplace inst clock_control_0 -pg 1 -lvl 1 -x 130 -y 230 -defaultsOSRD preplace netloc Top_0_io_led 1 2 1 NJ 310 -preplace netloc io_reset_1 1 0 2 NJ 300 NJ -preplace netloc io_clock_1 1 0 1 NJ 220 +preplace netloc Top_0_io_tx 1 2 1 550 130n +preplace netloc clock_control_0_clk_out 1 1 1 250 230n preplace netloc enable_clk_1 1 0 1 NJ 240 -preplace netloc processing_system7_0_DDR 1 2 1 NJ 60 -preplace netloc processing_system7_0_FIXED_IO 1 2 1 NJ 80 -levelinfo -pg 1 0 130 390 560 -pagesize -pg 1 -db -bbox -sgen -120 0 690 420 +preplace netloc io_clock_1 1 0 1 NJ 220 +preplace netloc io_reset_1 1 0 2 NJ 300 NJ +preplace netloc xlconstant_0_dout 1 1 1 250J 320n +preplace netloc processing_system7_0_FIXED_IO 1 2 1 550J 80n +preplace netloc processing_system7_0_DDR 1 2 1 550J 60n +levelinfo -pg 1 -10 130 400 570 +pagesize -pg 1 -db -bbox -sgen -130 0 700 420 " } @@ -872,11 +877,10 @@ cr_bd_design_1 "" set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ] set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ] -# call make_wrapper to create wrapper files +# make wrapper for design_1.db set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top] add_files -norecurse -fileset sources_1 $wrapper_path - # Create 'synth_1' run (if not found) if {[string equal [get_runs -quiet synth_1] ""]} { create_run -name synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 diff --git a/lab4/vivado/z710/riscv-z710-v2020.tcl b/lab4/vivado/z710/riscv-z710-v2020.tcl index dd04bb5..a68fb4e 100644 --- a/lab4/vivado/z710/riscv-z710-v2020.tcl +++ b/lab4/vivado/z710/riscv-z710-v2020.tcl @@ -3,7 +3,7 @@ # # riscv-z710-v2020.tcl: Tcl script for re-creating project 'riscv-z710-v2020' # -# Generated by Vivado on Mon Dec 25 11:27:52 +0800 2023 +# Generated by Vivado on Mon Nov 18 22:07:05 +0800 2024 # IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -23,14 +23,13 @@ # 2. The following source(s) files that were local or imported into the original project. # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) # -# +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710/riscv-z710-v2020/riscv-z710-v2020.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" # # 3. The following remote source files that were added to the original project:- # -# "E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v" -# "E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v" -# "E:/Workplace/2022-fall-yatcpu-repo/lab1/vivado/z710/pre-generate-files/v2020/design_1/hdl/design_1_wrapper.v" -# "E:/Workplace/2022-fall-yatcpu-repo/lab1/vivado/z710/z710.xdc" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710/Top.v" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710/clock_control.v" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710/z710.xdc" # #***************************************************************************************** @@ -131,9 +130,14 @@ set files [list \ [file normalize "${origin_dir}/../../verilog/z710/Top.v"] \ [file normalize "${origin_dir}/../../verilog/z710/clock_control.v"] \ ] -# [file normalize "${origin_dir}/pre-generate-files/v2020/design_1/hdl/design_1_wrapper.v"] \ add_files -norecurse -fileset $obj $files +# Import local files from the original project +# set files [list \ +# [file normalize "${origin_dir}/riscv-z710-v2020/riscv-z710-v2020.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" ]\ +# ] +# set imported_files [import_files -fileset sources_1 $files] + # Set 'sources_1' fileset file properties for remote files # None @@ -177,6 +181,7 @@ set obj [get_filesets sim_1] set obj [get_filesets sim_1] set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj set_property -name "top" -value "Top" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "top_file" -value "../../verilog/z710/Top.v" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj @@ -190,10 +195,10 @@ set obj [get_filesets utils_1] # Adding sources referenced in BDs, if not already added if { [get_files Top.v] == "" } { - import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v" + import_files -quiet -fileset sources_1 ../../verilog/z710/Top.v } if { [get_files clock_control.v] == "" } { - import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v" + import_files -quiet -fileset sources_1 ../../verilog/z710/clock_control.v } @@ -307,7 +312,7 @@ proc cr_bd_design_1 { parentCell } { # Create ports set enable_clk [ create_bd_port -dir I -type data enable_clk ] set io_alive_led [ create_bd_port -dir O io_alive_led ] - set io_clock [ create_bd_port -dir I -type clk -freq_hz 50000000 io_clock ] + set io_clock [ create_bd_port -dir I -type clk -freq_hz 125000000 io_clock ] set io_reset [ create_bd_port -dir I -type rst io_reset ] # Create instance: Top_0, and set properties @@ -405,7 +410,7 @@ proc cr_bd_design_1 { parentCell } { CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ CONFIG.PCW_ENET1_RESET_ENABLE {0} \ - CONFIG.PCW_ENET_RESET_ENABLE {1} \ + CONFIG.PCW_ENET_RESET_ENABLE {0} \ CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ CONFIG.PCW_ENET_RESET_SELECT {} \ CONFIG.PCW_USB0_USB0_IO {