init repo

lab1/src/test/scala/riscv/TestAnnotations.scala

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+// Copyright 2022 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv
+
+import chiseltest.{VerilatorBackendAnnotation, WriteVcdAnnotation}
+import firrtl.AnnotationSeq
+
+import java.nio.file.{Files, Paths}
+
+object VerilatorEnabler {
+  val annos: AnnotationSeq = if (sys.env.contains("Path")) {
+    if (sys.env.getOrElse("Path", "").split(";").exists(path => {
+      Files.exists(Paths.get(path, "verilator"))
+    })) {
+      Seq(VerilatorBackendAnnotation)
+    } else{
+      Seq()
+    }
+  } else {
+    if (sys.env.getOrElse("PATH", "").split(":").exists(path => {
+      Files.exists(Paths.get(path, "verilator"))
+    })) {
+      Seq(VerilatorBackendAnnotation)
+    } else {
+      Seq()
+    }
+  }
+}
+
+object WriteVcdEnabler {
+  val annos: AnnotationSeq = if (sys.env.contains("WRITE_VCD")) {
+    Seq(WriteVcdAnnotation)
+  } else {
+    Seq()
+  }
+}
+
+object TestAnnotations {
+  val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+}

lab1/src/test/scala/riscv/singlecycle/CPUTest.scala

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+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import peripheral.{InstructionROM, Memory, ROMLoader}
+import riscv.core.{CPU, ProgramCounter}
+import riscv.{Parameters, TestAnnotations}
+
+import java.nio.{ByteBuffer, ByteOrder}
+
+
+class TestTopModule(exeFilename: String) extends Module {
+  val io = IO(new Bundle {
+    val mem_debug_read_address = Input(UInt(Parameters.AddrWidth))
+    val regs_debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
+    val regs_debug_read_data = Output(UInt(Parameters.DataWidth))
+    val mem_debug_read_data = Output(UInt(Parameters.DataWidth))
+  })
+
+  val mem = Module(new Memory(8192))
+  val instruction_rom = Module(new InstructionROM(exeFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  rom_loader.io.rom_data := instruction_rom.io.data
+  rom_loader.io.load_address := Parameters.EntryAddress
+  instruction_rom.io.address := rom_loader.io.rom_address
+
+  val CPU_clkdiv = RegInit(UInt(2.W), 0.U)
+  val CPU_tick = Wire(Bool())
+  val CPU_next = Wire(UInt(2.W))
+  CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U)
+  CPU_tick := CPU_clkdiv === 0.U
+  CPU_clkdiv := CPU_next
+
+  withClock(CPU_tick.asClock) {
+    val cpu = Module(new CPU)
+    cpu.io.debug_read_address := 0.U
+    cpu.io.instruction_valid := rom_loader.io.load_finished
+    mem.io.instruction_address := cpu.io.instruction_address
+    cpu.io.instruction := mem.io.instruction
+
+
+    when(!rom_loader.io.load_finished) {
+      rom_loader.io.bundle <> mem.io.bundle
+      cpu.io.memory_bundle.read_data := 0.U
+    }.otherwise {
+      rom_loader.io.bundle.read_data := 0.U
+      cpu.io.memory_bundle <> mem.io.bundle
+    }
+
+    cpu.io.debug_read_address := io.regs_debug_read_address
+    io.regs_debug_read_data := cpu.io.debug_read_data
+  }
+
+  mem.io.debug_read_address := io.mem_debug_read_address
+  io.mem_debug_read_data := mem.io.debug_read_data
+}
+
+
+class FibonacciTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Single Cycle CPU"
+  it should "calculate recursively fibonacci(10)" in {
+    test(new TestTopModule("fibonacci.asmbin")).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+
+      c.io.mem_debug_read_address.poke(4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(55.U)
+    }
+  }
+}
+
+class QuicksortTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Single Cycle CPU"
+  it should "quicksort 10 numbers" in {
+    test(new TestTopModule("quicksort.asmbin")).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+      for (i <- 1 to 10) {
+        c.io.mem_debug_read_address.poke((4 * i).U)
+        c.clock.step()
+        c.io.mem_debug_read_data.expect((i - 1).U)
+      }
+    }
+  }
+}
+
+class ByteAccessTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Single Cycle CPU"
+  it should "store and load single byte" in {
+    test(new TestTopModule("sb.asmbin")).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 500) {
+        c.clock.step()
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+      c.io.regs_debug_read_address.poke(5.U)
+      c.io.regs_debug_read_data.expect(0xDEADBEEFL.U)
+      c.io.regs_debug_read_address.poke(6.U)
+      c.io.regs_debug_read_data.expect(0xEF.U)
+      c.io.regs_debug_read_address.poke(1.U)
+      c.io.regs_debug_read_data.expect(0x15EF.U)
+    }
+  }
+}

lab1/src/test/scala/riscv/singlecycle/ExecuteTest.scala

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+// Copyright 2022 hrpccs
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import riscv.TestAnnotations
+import riscv.core.{ALUOp1Source, ALUOp2Source, Execute, InstructionTypes}
+
+class ExecuteTest extends AnyFlatSpec with ChiselScalatestTester{
+  behavior of "Exxecute of Single Cycle CPU"
+  it should "execute correctly" in {
+    test(new Execute).withAnnotations(TestAnnotations.annos) { c =>
+
+      // add test
+      c.io.instruction.poke(0x001101b3L.U) //x3 =  x2 + x1
+      //c.io.immediate.poke(0.U)
+      //c.io.aluop1_source.poke(0.U)
+      //c.io.aluop2_source.poke(0.U)
+
+      var x = 0
+      for (x <- 0 to 100) {
+        val op1 = scala.util.Random.nextInt(429496729)
+        val op2 = scala.util.Random.nextInt(429496729)
+        val result = op1 + op2
+        val addr = scala.util.Random.nextInt(32)
+
+        c.io.reg1_data.poke(op1.U)
+        c.io.reg2_data.poke(op2.U)
+
+        c.clock.step()
+        c.io.mem_alu_result.expect(result.U)
+        c.io.if_jump_flag.expect(0.U)
+      }
+
+      // beq test
+      c.io.instruction.poke(0x00208163L.U) //pc + 2 if x1 === x2
+      c.io.instruction_address.poke(2.U)
+      c.io.immediate.poke(2.U)
+      c.io.aluop1_source.poke(1.U)
+      c.io.aluop2_source.poke(1.U)
+      c.clock.step()
+
+      // equ
+      c.io.reg1_data.poke(9.U)
+      c.io.reg2_data.poke(9.U)
+      c.clock.step()//add
+      c.io.if_jump_flag.expect(1.U)
+      c.io.if_jump_address.expect(4.U)
+
+      // not equ
+      c.io.reg1_data.poke(9.U)
+      c.io.reg2_data.poke(19.U)
+      c.clock.step()
+      c.io.if_jump_flag.expect(0.U)
+      c.io.if_jump_address.expect(4.U)
+    }
+  }
+}

lab1/src/test/scala/riscv/singlecycle/InstructionDecoderTest.scala

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+// Copyright 2022 hrpccs
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import riscv.TestAnnotations
+import riscv.core.{ALUOp1Source, ALUOp2Source, InstructionDecode, InstructionTypes}
+
+class InstructionDecoderTest extends AnyFlatSpec with ChiselScalatestTester{
+  behavior of "InstructionDecoder of Single Cycle CPU"
+  it should "produce correct control signal" in {
+    test(new InstructionDecode).withAnnotations(TestAnnotations.annos) { c =>
+      c.io.instruction.poke(0x00a02223L.U) //S-type
+      c.io.ex_aluop1_source.expect(ALUOp1Source.Register)
+      c.io.ex_aluop2_source.expect(ALUOp2Source.Immediate)
+      c.io.regs_reg1_read_address.expect(0.U)
+      c.io.regs_reg2_read_address.expect(10.U)
+      c.clock.step()
+
+      c.io.instruction.poke(0x000022b7L.U) //lui
+      c.io.regs_reg1_read_address.expect(0.U)
+      c.io.ex_aluop1_source.expect(ALUOp1Source.Register)
+      c.io.ex_aluop2_source.expect(ALUOp2Source.Immediate)
+      c.clock.step()
+
+      c.io.instruction.poke(0x002081b3L.U) //add
+      c.io.ex_aluop1_source.expect(ALUOp1Source.Register)
+      c.io.ex_aluop2_source.expect(ALUOp2Source.Register)
+      c.clock.step()
+    }
+  }
+}

lab1/src/test/scala/riscv/singlecycle/InstructionFetchTest.scala

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+// Copyright 2022 hrpccs
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import riscv.TestAnnotations
+import riscv.Parameters
+import riscv.core.{ALUOp1Source, ALUOp2Source, InstructionFetch, InstructionTypes,ProgramCounter}
+
+
+import scala.math.pow
+import scala.util.Random
+
+
+
+class InstructionFetchTest extends AnyFlatSpec with ChiselScalatestTester{
+  behavior of "InstructionFetch of Single Cycle CPU"
+  it should "fetch instruction" in {
+    test(new InstructionFetch).withAnnotations(TestAnnotations.annos) { c =>
+      val entry = 0x1000
+      var pre = entry
+      var cur = pre
+      c.io.instruction_valid.poke(true.B)
+      var x = 0
+      for (x <- 0 to 100) {
+        Random.nextInt(2) match {
+          case 0 => // no jump
+            cur = pre + 4
+            c.io.jump_flag_id.poke(false.B)
+            c.clock.step()
+            c.io.instruction_address.expect(cur)
+            pre = pre + 4
+          case 1 => // jump
+            c.io.jump_flag_id.poke(true.B)
+            c.io.jump_address_id.poke(entry)
+            c.clock.step()
+            c.io.instruction_address.expect(entry)
+            pre = entry
+        }
+      }
+
+      }
+    }
+}

lab1/src/test/scala/riscv/singlecycle/RegisterFileTest.scala

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+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import riscv.TestAnnotations
+import riscv.core.RegisterFile
+
+class RegisterFileTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Register File of Single Cycle CPU"
+  it should "read the written content" in {
+    test(new RegisterFile).withAnnotations(TestAnnotations.annos) { c =>
+      timescope {
+        c.io.write_enable.poke(true.B)
+        c.io.write_address.poke(1.U)
+        c.io.write_data.poke(0xDEADBEEFL.U)
+        c.clock.step()
+      }
+      c.io.read_address1.poke(1.U)
+      c.io.read_data1.expect(0xDEADBEEFL.U)
+    }
+  }
+
+  it should "x0 always be zero" in {
+    test(new RegisterFile).withAnnotations(TestAnnotations.annos) { c =>
+      timescope {
+        c.io.write_enable.poke(true.B)
+        c.io.write_address.poke(0.U)
+        c.io.write_data.poke(0xDEADBEEFL.U)
+        c.clock.step()
+      }
+      c.io.read_address1.poke(0.U)
+      c.io.read_data1.expect(0.U)
+    }
+  }
+
+  it should "read the writing content" in {
+    test(new RegisterFile).withAnnotations(TestAnnotations.annos) { c =>
+      timescope {
+        c.io.read_address1.poke(2.U)
+        c.io.read_data1.expect(0.U)
+        c.io.write_enable.poke(true.B)
+        c.io.write_address.poke(2.U)
+        c.io.write_data.poke(0xDEADBEEFL.U)
+        c.clock.step()
+        c.io.read_address1.poke(2.U)
+        c.io.read_data1.expect(0xDEADBEEFL.U)
+        c.clock.step()
+      }
+      c.io.read_address1.poke(2.U)
+      c.io.read_data1.expect(0xDEADBEEFL.U)
+    }
+  }
+
+}