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Deleted useless verilog files

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PurplePower
2023-12-26 01:18:54 +08:00
parent 816f894007
commit 844cb062c2
17 changed files with 0 additions and 520 deletions
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32
lab4/verilog/z710/Top_reset.v
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@@ -1,32 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/12/01 16:32:40
// Design Name:
// Module Name: Top_reset
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top_reset(
input reset
);
initial begin
reset = 1;
#25 reset = 0;
end
endmodule

28
lab4/verilog/z710/pass_through.v
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@@ -1,28 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/11/29 16:38:00
// Design Name:
// Module Name: pass_through
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pass_through(
input in,
output out
);
assign out = in;
endmodule

35
lab4/verilog/z710/test.v
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@@ -1,35 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2021/12/17 16:31:05
// Design Name:
// Module Name: test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module test();
reg clock;
reg reset;
initial begin
clock = 0;
forever #1 clock = ~clock;
end
initial begin
reset = 1;
#2 reset = 0;
end
Top top(clock, reset);
endmodule

30
lab4/verilog/z710/uart_control.v
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@@ -1,30 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/11/30 00:51:08
// Design Name:
// Module Name: uart_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_control(
input enable_uart,
input tx_in,
output tx_out
);
assign tx_out = (enable_uart) ? tx_in : 1'h1;
endmodule