diff --git a/lab1/verilog/z710/Top_reset.v b/lab1/verilog/z710/Top_reset.v deleted file mode 100644 index 4349e47..0000000 --- a/lab1/verilog/z710/Top_reset.v +++ /dev/null @@ -1,32 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/12/01 16:32:40 -// Design Name: -// Module Name: Top_reset -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module Top_reset( - input reset - ); - initial begin - reset = 1; - #25 reset = 0; - end - - -endmodule diff --git a/lab1/verilog/z710/pass_through.v b/lab1/verilog/z710/pass_through.v deleted file mode 100644 index daf212e..0000000 --- a/lab1/verilog/z710/pass_through.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/11/29 16:38:00 -// Design Name: -// Module Name: pass_through -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module pass_through( - input in, - output out - ); - assign out = in; -endmodule diff --git a/lab1/verilog/z710/uart_control.v b/lab1/verilog/z710/uart_control.v deleted file mode 100644 index a73b6d2..0000000 --- a/lab1/verilog/z710/uart_control.v +++ /dev/null @@ -1,30 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/11/30 00:51:08 -// Design Name: -// Module Name: uart_control -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module uart_control( - input enable_uart, - input tx_in, - output tx_out - ); - assign tx_out = (enable_uart) ? tx_in : 1'h1; - -endmodule diff --git a/lab2/verilog/z710/Top_reset.v b/lab2/verilog/z710/Top_reset.v deleted file mode 100644 index 4349e47..0000000 --- a/lab2/verilog/z710/Top_reset.v +++ /dev/null @@ -1,32 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/12/01 16:32:40 -// Design Name: -// Module Name: Top_reset -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module Top_reset( - input reset - ); - initial begin - reset = 1; - #25 reset = 0; - end - - -endmodule diff --git a/lab2/verilog/z710/pass_through.v b/lab2/verilog/z710/pass_through.v deleted file mode 100644 index daf212e..0000000 --- a/lab2/verilog/z710/pass_through.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/11/29 16:38:00 -// Design Name: -// Module Name: pass_through -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module pass_through( - input in, - output out - ); - assign out = in; -endmodule diff --git a/lab2/verilog/z710/uart_control.v b/lab2/verilog/z710/uart_control.v deleted file mode 100644 index a73b6d2..0000000 --- a/lab2/verilog/z710/uart_control.v +++ /dev/null @@ -1,30 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/11/30 00:51:08 -// Design Name: -// Module Name: uart_control -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module uart_control( - input enable_uart, - input tx_in, - output tx_out - ); - assign tx_out = (enable_uart) ? tx_in : 1'h1; - -endmodule diff --git a/lab3/verilog/z710/Top_reset.v b/lab3/verilog/z710/Top_reset.v deleted file mode 100644 index 4349e47..0000000 --- a/lab3/verilog/z710/Top_reset.v +++ /dev/null @@ -1,32 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/12/01 16:32:40 -// Design Name: -// Module Name: Top_reset -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module Top_reset( - input reset - ); - initial begin - reset = 1; - #25 reset = 0; - end - - -endmodule diff --git a/lab3/verilog/z710/pass_through.v b/lab3/verilog/z710/pass_through.v deleted file mode 100644 index daf212e..0000000 --- a/lab3/verilog/z710/pass_through.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/11/29 16:38:00 -// Design Name: -// Module Name: pass_through -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module pass_through( - input in, - output out - ); - assign out = in; -endmodule diff --git a/lab3/verilog/z710/test.v b/lab3/verilog/z710/test.v deleted file mode 100644 index b250a66..0000000 --- a/lab3/verilog/z710/test.v +++ /dev/null @@ -1,35 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2021/12/17 16:31:05 -// Design Name: -// Module Name: test -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module test(); -reg clock; -reg reset; -initial begin -clock = 0; -forever #1 clock = ~clock; -end -initial begin -reset = 1; -#2 reset = 0; -end -Top top(clock, reset); -endmodule \ No newline at end of file diff --git a/lab3/verilog/z710/uart_control.v b/lab3/verilog/z710/uart_control.v deleted file mode 100644 index a73b6d2..0000000 --- a/lab3/verilog/z710/uart_control.v +++ /dev/null @@ -1,30 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/11/30 00:51:08 -// Design Name: -// Module Name: uart_control -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module uart_control( - input enable_uart, - input tx_in, - output tx_out - ); - assign tx_out = (enable_uart) ? tx_in : 1'h1; - -endmodule diff --git a/lab4/verilog/z710/Top_reset.v b/lab4/verilog/z710/Top_reset.v deleted file mode 100644 index 4349e47..0000000 --- a/lab4/verilog/z710/Top_reset.v +++ /dev/null @@ -1,32 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/12/01 16:32:40 -// Design Name: -// Module Name: Top_reset -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module Top_reset( - input reset - ); - initial begin - reset = 1; - #25 reset = 0; - end - - -endmodule diff --git a/lab4/verilog/z710/pass_through.v b/lab4/verilog/z710/pass_through.v deleted file mode 100644 index daf212e..0000000 --- a/lab4/verilog/z710/pass_through.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/11/29 16:38:00 -// Design Name: -// Module Name: pass_through -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module pass_through( - input in, - output out - ); - assign out = in; -endmodule diff --git a/lab4/verilog/z710/test.v b/lab4/verilog/z710/test.v deleted file mode 100644 index b250a66..0000000 --- a/lab4/verilog/z710/test.v +++ /dev/null @@ -1,35 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2021/12/17 16:31:05 -// Design Name: -// Module Name: test -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module test(); -reg clock; -reg reset; -initial begin -clock = 0; -forever #1 clock = ~clock; -end -initial begin -reset = 1; -#2 reset = 0; -end -Top top(clock, reset); -endmodule \ No newline at end of file diff --git a/lab4/verilog/z710/uart_control.v b/lab4/verilog/z710/uart_control.v deleted file mode 100644 index a73b6d2..0000000 --- a/lab4/verilog/z710/uart_control.v +++ /dev/null @@ -1,30 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/11/30 00:51:08 -// Design Name: -// Module Name: uart_control -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module uart_control( - input enable_uart, - input tx_in, - output tx_out - ); - assign tx_out = (enable_uart) ? tx_in : 1'h1; - -endmodule diff --git a/mini-yatcpu/verilog/z710/Top_reset.v b/mini-yatcpu/verilog/z710/Top_reset.v deleted file mode 100644 index 4349e47..0000000 --- a/mini-yatcpu/verilog/z710/Top_reset.v +++ /dev/null @@ -1,32 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/12/01 16:32:40 -// Design Name: -// Module Name: Top_reset -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module Top_reset( - input reset - ); - initial begin - reset = 1; - #25 reset = 0; - end - - -endmodule diff --git a/mini-yatcpu/verilog/z710/pass_through.v b/mini-yatcpu/verilog/z710/pass_through.v deleted file mode 100644 index daf212e..0000000 --- a/mini-yatcpu/verilog/z710/pass_through.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/11/29 16:38:00 -// Design Name: -// Module Name: pass_through -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module pass_through( - input in, - output out - ); - assign out = in; -endmodule diff --git a/mini-yatcpu/verilog/z710/uart_control.v b/mini-yatcpu/verilog/z710/uart_control.v deleted file mode 100644 index a73b6d2..0000000 --- a/mini-yatcpu/verilog/z710/uart_control.v +++ /dev/null @@ -1,30 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/11/30 00:51:08 -// Design Name: -// Module Name: uart_control -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module uart_control( - input enable_uart, - input tx_in, - output tx_out - ); - assign tx_out = (enable_uart) ? tx_in : 1'h1; - -endmodule