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lab3跑完

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handsomezhuzhu
2025-10-13 18:01:48 +08:00
parent 37ced72a9d
commit 81adb30885
1 changed files with 8 additions and 1 deletions
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9
lab3/src/main/scala/riscv/core/fivestage_final/Control.scala
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@@ -44,8 +44,15 @@ class Control extends Module {
val id_jump_needs_ex_alu = io.jump_instruction_id && io.rd_ex =/= 0.U && val id_jump_needs_ex_alu = io.jump_instruction_id && io.rd_ex =/= 0.U &&
!io.memory_read_enable_ex && // 确保不是load-use hazard !io.memory_read_enable_ex && // 确保不是load-use hazard
(io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id) (io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id)
// 当ID阶段的分支/跳转依赖于MEM阶段的一条load指令结果时，必须阻塞，
// 因为此时无法从MEM阶段获得真实的读数据（仅有ALU地址）。
val id_jump_needs_mem_load = io.jump_instruction_id && io.memory_read_enable_mem && io.rd_mem =/= 0.U &&
(io.rd_mem === io.rs1_id || io.rd_mem === io.rs2_id)
// 最终的阻塞条件 // 最终的阻塞条件
stall := load_use_hazard || id_jump_needs_ex_alu stall := load_use_hazard || id_jump_needs_ex_alu || id_jump_needs_mem_load
// 只有在流水线不被阻塞时，跳转信号（flush）才应该生效。 // 只有在流水线不被阻塞时，跳转信号（flush）才应该生效。
val flush = io.jump_flag && !stall val flush = io.jump_flag && !stall
// 最终输出 // 最终输出