From 81adb308853408ffcf50fbc22532bb0a4c6a998b Mon Sep 17 00:00:00 2001
From: handsomezhuzhu <2658601135@qq.com>
Date: Mon, 13 Oct 2025 18:01:48 +0800
Subject: [PATCH] =?UTF-8?q?lab3=E8=B7=91=E5=AE=8C?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 .../main/scala/riscv/core/fivestage_final/Control.scala  | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/lab3/src/main/scala/riscv/core/fivestage_final/Control.scala b/lab3/src/main/scala/riscv/core/fivestage_final/Control.scala
index 2cf6dc4..662f035 100644
--- a/lab3/src/main/scala/riscv/core/fivestage_final/Control.scala
+++ b/lab3/src/main/scala/riscv/core/fivestage_final/Control.scala
@@ -44,8 +44,15 @@ class Control extends Module {
   val id_jump_needs_ex_alu = io.jump_instruction_id && io.rd_ex =/= 0.U &&
     !io.memory_read_enable_ex && // 确保不是load-use hazard
     (io.rd_ex === io.rs1_id || io.rd_ex === io.rs2_id)
+
+  // 当ID阶段的分支/跳转依赖于MEM阶段的一条load指令结果时，必须阻塞，
+  // 因为此时无法从MEM阶段获得真实的读数据（仅有ALU地址）。
+  val id_jump_needs_mem_load = io.jump_instruction_id && io.memory_read_enable_mem && io.rd_mem =/= 0.U &&
+    (io.rd_mem === io.rs1_id || io.rd_mem === io.rs2_id)
+
   // 最终的阻塞条件
-  stall := load_use_hazard || id_jump_needs_ex_alu
+  stall := load_use_hazard || id_jump_needs_ex_alu || id_jump_needs_mem_load
+
   // 只有在流水线不被阻塞时，跳转信号（flush）才应该生效。
   val flush = io.jump_flag && !stall
   // 最终输出