added vivado-vitis uart workflow to lab3

lab3/verilog/z710/clock_control.v

@@ -25,5 +25,22 @@ module clock_control(
     input enable_clk,
     output clk_out
     );
-    assign clk_out = clk_in & enable_clk;
+    
+    // if clock is divided
+    localparam clk_div = 2; // clock is diveded by half of divisor
+    reg [3:0] cnt = 4'd0;
+    reg out = 1'b0;
+    always @(posedge clk_in) begin 
+        cnt <= cnt + 4'd1;
+        if (cnt >= (clk_div - 1)) begin
+            out <= ~out;
+            cnt <= 0;
+        end
+    end
+    assign clk_out = out & enable_clk;
+    
+    
+    // original clock
+//    assign clk_out = clk_in & enable_clk;
+    
 endmodule