From 5ecb75157a5af1b95314cc08c1ed0abdac414d1a Mon Sep 17 00:00:00 2001 From: PurplePower <60787289+PurplePower@users.noreply.github.com> Date: Mon, 25 Dec 2023 23:40:26 +0800 Subject: [PATCH] added vivado-vitis uart workflow to lab3 --- lab3/verilog/z710/clock_control.v | 19 +- lab3/verilog/z710/design_1.bd | 459 ------- lab3/verilog/z710/design_1_wrapper.v | 116 -- lab3/vivado/z710/README.md | 99 ++ lab3/vivado/z710/generate_and_program.tcl | 17 - lab3/vivado/z710/generate_bitstream.tcl | 8 +- lab3/vivado/z710/open_project.tcl | 35 +- lab3/vivado/z710/program_device.tcl | 24 - lab3/vivado/z710/riscv-z710-v2020.tcl | 1170 +++++++++++++++++ .../z710/riscv-z710/design_1_wrapper.xsa | Bin 346664 -> 0 bytes .../sources_1/bd/design_1/design_1.bd | 459 ------- .../bd/design_1/hdl/design_1_wrapper.v | 116 -- lab3/vivado/z710/riscv-z710/riscv-z710.xpr | 376 ------ lab3/vivado/z710/vitis_prj_run.tcl | 83 ++ 14 files changed, 1379 insertions(+), 1602 deletions(-) delete mode 100644 lab3/verilog/z710/design_1.bd delete mode 100644 lab3/verilog/z710/design_1_wrapper.v create mode 100644 lab3/vivado/z710/README.md delete mode 100644 lab3/vivado/z710/generate_and_program.tcl delete mode 100644 lab3/vivado/z710/program_device.tcl create mode 100644 lab3/vivado/z710/riscv-z710-v2020.tcl delete mode 100644 lab3/vivado/z710/riscv-z710/design_1_wrapper.xsa delete mode 100644 lab3/vivado/z710/riscv-z710/riscv-z710.srcs/sources_1/bd/design_1/design_1.bd delete mode 100644 lab3/vivado/z710/riscv-z710/riscv-z710.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v delete mode 100644 lab3/vivado/z710/riscv-z710/riscv-z710.xpr create mode 100644 lab3/vivado/z710/vitis_prj_run.tcl diff --git a/lab3/verilog/z710/clock_control.v b/lab3/verilog/z710/clock_control.v index f4e882d..30bc6e5 100644 --- a/lab3/verilog/z710/clock_control.v +++ b/lab3/verilog/z710/clock_control.v @@ -25,5 +25,22 @@ module clock_control( input enable_clk, output clk_out ); - assign clk_out = clk_in & enable_clk; + + // if clock is divided + localparam clk_div = 2; // clock is diveded by half of divisor + reg [3:0] cnt = 4'd0; + reg out = 1'b0; + always @(posedge clk_in) begin + cnt <= cnt + 4'd1; + if (cnt >= (clk_div - 1)) begin + out <= ~out; + cnt <= 0; + end + end + assign clk_out = out & enable_clk; + + + // original clock +// assign clk_out = clk_in & enable_clk; + endmodule diff --git a/lab3/verilog/z710/design_1.bd b/lab3/verilog/z710/design_1.bd deleted file mode 100644 index 39f979a..0000000 --- a/lab3/verilog/z710/design_1.bd +++ /dev/null @@ -1,459 +0,0 @@ -{ - "design": { - "design_info": { - "boundary_crc": "0xD2682A7282870375", - "device": "xc7z010clg400-1", - "name": "design_1", - "rev_ctrl_bd_flag": "RevCtrlBdOff", - "synth_flow_mode": "Hierarchical", - "tool_version": "2020.1", - "validated": "true" - }, - "design_tree": { - "processing_system7_0": "", - "clock_control_0": "", - "xlconstant_0": "", - "Top_0": "" - }, - "interface_ports": { - "DDR": { - "mode": "Master", - "vlnv": "xilinx.com:interface:ddrx_rtl:1.0", - "parameters": { - "CAN_DEBUG": { - "value": "false", - "value_src": "default" - }, - "TIMEPERIOD_PS": { - "value": "1250", - "value_src": "default" - }, - "MEMORY_TYPE": { - "value": "COMPONENTS", - "value_src": "default" - }, - "DATA_WIDTH": { - "value": "8", - "value_src": "default" - }, - "CS_ENABLED": { - "value": "true", - "value_src": "default" - }, - "DATA_MASK_ENABLED": { - "value": "true", - "value_src": "default" - }, - "SLOT": { - "value": "Single", - "value_src": "default" - }, - "MEM_ADDR_MAP": { - "value": "ROW_COLUMN_BANK", - "value_src": "default" - }, - "BURST_LENGTH": { - "value": "8", - "value_src": "default" - }, - "AXI_ARBITRATION_SCHEME": { - "value": "TDM", - "value_src": "default" - }, - "CAS_LATENCY": { - "value": "11", - "value_src": "default" - }, - "CAS_WRITE_LATENCY": { - "value": "11", - "value_src": "default" - } - } - }, - "FIXED_IO": { - "mode": "Master", - "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0", - "parameters": { - "CAN_DEBUG": { - "value": "false", - "value_src": "default" - } - } - } - }, - "ports": { - "io_clock": { - "type": "clk", - "direction": "I", - "parameters": { - "CLK_DOMAIN": { - "value": "design_1_clock", - "value_src": "default" - }, - "FREQ_HZ": { - "value": "100000000" - }, - "FREQ_TOLERANCE_HZ": { - "value": "0", - "value_src": "default" - }, - "INSERT_VIP": { - "value": "0", - "value_src": "default" - }, - "PHASE": { - "value": "0.000", - "value_src": "default" - } - } - }, - "io_alive_led": { - "direction": "O" - }, - "io_reset": { - "direction": "I", - "parameters": { - "POLARITY": { - "value": "", - "value_src": "weak" - } - } - }, - "enable_clk": { - "type": "clk", - "direction": "I", - "parameters": { - "CLK_DOMAIN": { - "value": "design_1_enable_clk_0", - "value_src": "default" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "default" - }, - "FREQ_TOLERANCE_HZ": { - "value": "0", - "value_src": "default" - }, - "INSERT_VIP": { - "value": "0", - "value_src": "default" - }, - "PHASE": { - "value": "0.000", - "value_src": "default" - } - } - } - }, - "components": { - "processing_system7_0": { - "vlnv": "xilinx.com:ip:processing_system7:5.5", - "xci_name": "design_1_processing_system7_0_0", - "parameters": { - "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { - "value": "666.666687" - }, - "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { - "value": "10.000000" - }, - "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { - "value": "10.158730" - }, - "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": { - "value": "10.000000" - }, - "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": { - "value": "10.000000" - }, - "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { - "value": "50.000000" - }, - "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { - "value": "10.000000" - }, - "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": { - "value": "10.000000" - }, - "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": { - "value": "10.000000" - }, - "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": { - "value": "200.000000" - }, - "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": { - "value": "10.000000" - }, - "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": { - "value": "10.000000" - }, - "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": { - "value": "10.000000" - }, - "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": { - "value": "10.000000" - }, - "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": { - "value": "200.000000" - }, - "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": { - "value": "111.111115" - }, - "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": { - "value": "111.111115" - }, - "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": { - "value": "111.111115" - }, - "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": { - "value": "111.111115" - }, - "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": { - "value": "111.111115" - }, - "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": { - "value": "111.111115" - }, - "PCW_ACT_UART_PERIPHERAL_FREQMHZ": { - "value": "100.000000" - }, - "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": { - "value": "111.111115" - }, - "PCW_CLK0_FREQ": { - "value": "50000000" - }, - "PCW_CLK1_FREQ": { - "value": "10000000" - }, - "PCW_CLK2_FREQ": { - "value": "10000000" - }, - "PCW_CLK3_FREQ": { - "value": "10000000" - }, - "PCW_DDR_RAM_HIGHADDR": { - "value": "0x1FFFFFFF" - }, - "PCW_EN_EMIO_UART0": { - "value": "1" - }, - "PCW_EN_UART0": { - "value": "1" - }, - "PCW_EN_UART1": { - "value": "1" - }, - "PCW_FPGA_FCLK0_ENABLE": { - "value": "1" - }, - "PCW_MIO_48_IOTYPE": { - "value": "LVCMOS 3.3V" - }, - "PCW_MIO_48_PULLUP": { - "value": "enabled" - }, - "PCW_MIO_48_SLEW": { - "value": "slow" - }, - "PCW_MIO_49_IOTYPE": { - "value": "LVCMOS 3.3V" - }, - "PCW_MIO_49_PULLUP": { - "value": "enabled" - }, - "PCW_MIO_49_SLEW": { - "value": "slow" - }, - "PCW_MIO_TREE_PERIPHERALS": { - "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned" - }, - "PCW_MIO_TREE_SIGNALS": { - "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned" - }, - "PCW_UART0_GRP_FULL_ENABLE": { - "value": "0" - }, - "PCW_UART0_PERIPHERAL_ENABLE": { - "value": "1" - }, - "PCW_UART0_UART0_IO": { - "value": "EMIO" - }, - "PCW_UART1_GRP_FULL_ENABLE": { - "value": "0" - }, - "PCW_UART1_PERIPHERAL_ENABLE": { - "value": "1" - }, - "PCW_UART1_UART1_IO": { - "value": "MIO 48 .. 49" - }, - "PCW_UART_PERIPHERAL_FREQMHZ": { - "value": "100" - }, - "PCW_UART_PERIPHERAL_VALID": { - "value": "1" - }, - "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": { - "value": "533.333374" - }, - "PCW_USE_M_AXI_GP0": { - "value": "0" - } - } - }, - "clock_control_0": { - "vlnv": "xilinx.com:module_ref:clock_control:1.0", - "xci_name": "design_1_clock_control_0_0", - "reference_info": { - "ref_type": "hdl", - "ref_name": "clock_control", - "boundary_crc": "0x0" - }, - "ports": { - "clk_in": { - "direction": "I", - "parameters": { - "CLK_DOMAIN": { - "value": "design_1_clock", - "value_src": "default_prop" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "user_prop" - }, - "PHASE": { - "value": "0.000", - "value_src": "default_prop" - } - } - }, - "enable_clk": { - "type": "clk", - "direction": "I", - "parameters": { - "CLK_DOMAIN": { - "value": "design_1_enable_clk_0", - "value_src": "default_prop" - } - } - }, - "clk_out": { - "direction": "O", - "parameters": { - "CLK_DOMAIN": { - "value": "", - "value_src": "weak" - }, - "FREQ_HZ": { - "value": "", - "value_src": "weak" - }, - "PHASE": { - "value": "", - "value_src": "weak" - } - } - } - } - }, - "xlconstant_0": { - "vlnv": "xilinx.com:ip:xlconstant:1.1", - "xci_name": "design_1_xlconstant_0_0" - }, - "Top_0": { - "vlnv": "xilinx.com:module_ref:Top:1.0", - "xci_name": "design_1_Top_0_0", - "reference_info": { - "ref_type": "hdl", - "ref_name": "Top", - "boundary_crc": "0x0" - }, - "ports": { - "clock": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_RESET": { - "value": "reset", - "value_src": "constant" - } - } - }, - "reset": { - "type": "rst", - "direction": "I" - }, - "io_led": { - "direction": "O" - }, - "io_tx": { - "direction": "O" - }, - "io_rx": { - "direction": "I" - } - } - } - }, - "interface_nets": { - "processing_system7_0_DDR": { - "interface_ports": [ - "DDR", - "processing_system7_0/DDR" - ] - }, - "processing_system7_0_FIXED_IO": { - "interface_ports": [ - "FIXED_IO", - "processing_system7_0/FIXED_IO" - ] - } - }, - "nets": { - "Top_0_io_tx": { - "ports": [ - "Top_0/io_tx", - "processing_system7_0/UART0_RX" - ] - }, - "Top_0_io_led": { - "ports": [ - "Top_0/io_led", - "io_alive_led" - ] - }, - "io_reset_1": { - "ports": [ - "io_reset", - "Top_0/reset" - ] - }, - "io_clock_1": { - "ports": [ - "io_clock", - "clock_control_0/clk_in" - ] - }, - "enable_clk_0_1": { - "ports": [ - "enable_clk", - "clock_control_0/enable_clk" - ] - }, - "clock_control_0_clk_out": { - "ports": [ - "clock_control_0/clk_out", - "Top_0/clock" - ] - }, - "xlconstant_0_dout": { - "ports": [ - "xlconstant_0/dout", - "Top_0/io_rx" - ] - } - } - } -} \ No newline at end of file diff --git a/lab3/verilog/z710/design_1_wrapper.v b/lab3/verilog/z710/design_1_wrapper.v deleted file mode 100644 index e148ca7..0000000 --- a/lab3/verilog/z710/design_1_wrapper.v +++ /dev/null @@ -1,116 +0,0 @@ -//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -//-------------------------------------------------------------------------------- -//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 -//Date : Sun Dec 10 14:11:15 2023 -//Host : Tokisakix running 64-bit major release (build 9200) -//Command : generate_target design_1_wrapper.bd -//Design : design_1_wrapper -//Purpose : IP block netlist -//-------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -module design_1_wrapper - (DDR_addr, - DDR_ba, - DDR_cas_n, - DDR_ck_n, - DDR_ck_p, - DDR_cke, - DDR_cs_n, - DDR_dm, - DDR_dq, - DDR_dqs_n, - DDR_dqs_p, - DDR_odt, - DDR_ras_n, - DDR_reset_n, - DDR_we_n, - FIXED_IO_ddr_vrn, - FIXED_IO_ddr_vrp, - FIXED_IO_mio, - FIXED_IO_ps_clk, - FIXED_IO_ps_porb, - FIXED_IO_ps_srstb, - enable_clk, - io_alive_led, - io_clock, - io_reset); - inout [14:0]DDR_addr; - inout [2:0]DDR_ba; - inout DDR_cas_n; - inout DDR_ck_n; - inout DDR_ck_p; - inout DDR_cke; - inout DDR_cs_n; - inout [3:0]DDR_dm; - inout [31:0]DDR_dq; - inout [3:0]DDR_dqs_n; - inout [3:0]DDR_dqs_p; - inout DDR_odt; - inout DDR_ras_n; - inout DDR_reset_n; - inout DDR_we_n; - inout FIXED_IO_ddr_vrn; - inout FIXED_IO_ddr_vrp; - inout [53:0]FIXED_IO_mio; - inout FIXED_IO_ps_clk; - inout FIXED_IO_ps_porb; - inout FIXED_IO_ps_srstb; - input enable_clk; - output io_alive_led; - input io_clock; - input io_reset; - - wire [14:0]DDR_addr; - wire [2:0]DDR_ba; - wire DDR_cas_n; - wire DDR_ck_n; - wire DDR_ck_p; - wire DDR_cke; - wire DDR_cs_n; - wire [3:0]DDR_dm; - wire [31:0]DDR_dq; - wire [3:0]DDR_dqs_n; - wire [3:0]DDR_dqs_p; - wire DDR_odt; - wire DDR_ras_n; - wire DDR_reset_n; - wire DDR_we_n; - wire FIXED_IO_ddr_vrn; - wire FIXED_IO_ddr_vrp; - wire [53:0]FIXED_IO_mio; - wire FIXED_IO_ps_clk; - wire FIXED_IO_ps_porb; - wire FIXED_IO_ps_srstb; - wire enable_clk; - wire io_alive_led; - wire io_clock; - wire io_reset; - - design_1 design_1_i - (.DDR_addr(DDR_addr), - .DDR_ba(DDR_ba), - .DDR_cas_n(DDR_cas_n), - .DDR_ck_n(DDR_ck_n), - .DDR_ck_p(DDR_ck_p), - .DDR_cke(DDR_cke), - .DDR_cs_n(DDR_cs_n), - .DDR_dm(DDR_dm), - .DDR_dq(DDR_dq), - .DDR_dqs_n(DDR_dqs_n), - .DDR_dqs_p(DDR_dqs_p), - .DDR_odt(DDR_odt), - .DDR_ras_n(DDR_ras_n), - .DDR_reset_n(DDR_reset_n), - .DDR_we_n(DDR_we_n), - .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), - .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), - .FIXED_IO_mio(FIXED_IO_mio), - .FIXED_IO_ps_clk(FIXED_IO_ps_clk), - .FIXED_IO_ps_porb(FIXED_IO_ps_porb), - .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), - .enable_clk(enable_clk), - .io_alive_led(io_alive_led), - .io_clock(io_clock), - .io_reset(io_reset)); -endmodule diff --git a/lab3/vivado/z710/README.md b/lab3/vivado/z710/README.md new file mode 100644 index 0000000..18a60aa --- /dev/null +++ b/lab3/vivado/z710/README.md @@ -0,0 +1,99 @@ + +# 如何使用脚本使 CPU 烧录至 Zybo Z7-10 开发板并读取 UART 输出至电脑 + + +步骤如下： + +此处用 `vivado` 和 `xsct` 工具，并假设您已在 `vivado/z710` 目录下打开终端。（TODO） + +## 1. 生成 Vivado 项目 + +确保您的 `verilog/z710` 下已生成 Top.v ，且其他组件的 verilog 文件都存在。 +执行命令以生成设计： + +```pwsh +vivado -mode batch -source ./riscv-z710-v2020.tcl +``` + +完成后，您应见文件夹 `vivado/z710/riscv-z710-v2020`，且其中有 `riscv-z710-v2020.xpr`。 + + + +## 2. 生成比特流并导出硬件平台 + +完成上一步骤后，执行命令以生成比特流、导出硬件平台 .xsa 文件。 + +```pwsh +vivado -mode batch -source ./generate_bitstream.tcl +``` + +完成后，您应见 `vivado\z710\riscv-z710-v2020\design_1_wrapper.xsa` 文件。 + + +## 3. 构建 Vitis 项目并烧录至开发板 + +完成上一步骤后，将开发板连接至电脑，并开启电源。随后执行命令将 CPU 烧录至开发板，并使 Zynq 处理器监听并返回 UART 输出： + +```pwsh +xsct ./vitis_prj_run.tcl +``` + +若成功，您应看到开发板的 LD0 灯在打开其下方的 G15 开关（该开关控制输入CPU的时钟开关）时会闪烁，同时右侧 BTN16 上方的 LD12 已烧录指示灯亮起为绿色。 + +打开任意的 COM 通信工具，连接至合适串口，即可收到 CPU 的输出 UART 信息，按 BTN0 （K18）会重置 CPU 以重新打印。 + + + +## For Maintainers + +该段描述这些脚本如何获得，若您希望了解其中原理或做出贡献，可以阅读本节。 + +### lab3 auxiliary file related + +CPU 输入频率4分频。 + +### Use with Vivado 2020.1 + +#### Vivado 项目重建脚本 + +2020 版本的 Vivado 导出仍会引用 .bd 块设计文件（2022不会），即使勾选了用 TCL 重建块设计。从 Vivado 2022 版那里导出的脚本薅来一段代码让它不必引用 .bd 文件，从而单个文件就能重建项目。 + +用 Vivado 2020 的 Write Project Tcl 导出脚本后，开头会提示需要的文件，包括了块设计的 `design_1_wrapper.v`，但里面其实已经有 TCL 连线。 + +1. 在 `Set 'sources_1' fileset object` （Line 128）附近删除添加 `design_1_wrapper.v` 的一行 +2. 在注释`End of cr_bd_design_1()` 后，运行完 `cr_bd_design_ ""` 之后（Line 870），添加生成 wrapper Verilog 文件的指令，如下 +```tcl +... +# End of cr_bd_design_1() +cr_bd_design_1 "" +set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ] +set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ] + +# 加在这： call make_wrapper to create wrapper files +set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top] +add_files -norecurse -fileset sources_1 $wrapper_path +``` + +修改后上述脚本就能重建项目。 + +`open_project.tcl` 直接打开项目的 .xpr 项目文件，`generate_bitstream.tcl` 再生成比特流，并额外导出硬件平台。 + +#### Vitis 项目重建脚本 + +Vitis 仅在控制台的 Platform 控制台打印一些对硬件平台的操作指令，其他指令需要参照 XSCT（Xilinx Software Commandline Tool） 参考手册，以使用相关指令（纯苦工活）。一些流程在 Vitis IDE 里面的设置可以找到，比如 PS7 处理器的初始化流程（在脚本注释有写）。 + +XSCT 会单独使用一个 cmd 窗口执行，因此如果中途因错误退出将来不及看到任何错误信息，因此需要在命令行打开 xsct（如 `E:\Xilinx\Vitis\2020.1\bin\xsct`），然后逐行执行（多行的 if 结构可一次性复制多行），并查看错误。 + +注意 Vivado 和 Vitis 版本要一致，不要混用不同年份的版本。 + +*** + +### Use with Vivado 2022.1 + +#### Vivado 项目重建脚本 + +导（出）就完啦！ + +#### Vitis 项目重建脚本 + +应该和 2020 的一样。 \ No newline at end of file diff --git a/lab3/vivado/z710/generate_and_program.tcl b/lab3/vivado/z710/generate_and_program.tcl deleted file mode 100644 index 71df1af..0000000 --- a/lab3/vivado/z710/generate_and_program.tcl +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2021 Howard Lau -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# Only tested on Vivado 2020.1 on Windows 10 -source generate_bitstream.tcl -source program_device.tcl \ No newline at end of file diff --git a/lab3/vivado/z710/generate_bitstream.tcl b/lab3/vivado/z710/generate_bitstream.tcl index 4506c23..6b98552 100644 --- a/lab3/vivado/z710/generate_bitstream.tcl +++ b/lab3/vivado/z710/generate_bitstream.tcl @@ -54,8 +54,8 @@ while 1 { wait_on_run impl_1 -# copy the bitstream so vivado GUI still finds it -file copy riscv-z710/riscv-z710.runs/impl_1/design_1_wrapper.bit riscv-z710/riscv-z710.runs/impl_1/Top.bit -# this will export platform .xsz -write_hw_platform -fixed -include_bit -force -file ./riscv-z710/Top.xsa +# export hardware platform to Vitis +set_property pfm_name {} [get_files -all $project_dir/$project_name.srcs/sources_1/bd/design_1/design_1.bd] +write_hw_platform -fixed -include_bit -force -file $project_dir/design_1_wrapper.xsa + diff --git a/lab3/vivado/z710/open_project.tcl b/lab3/vivado/z710/open_project.tcl index f758198..2933802 100644 --- a/lab3/vivado/z710/open_project.tcl +++ b/lab3/vivado/z710/open_project.tcl @@ -1,33 +1,8 @@ -# Copyright 2021 Howard Lau -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# Only tested on Vivado 2020.1 on Windows 10 +# setup variables +set project_dir "./riscv-z710-v2020" +set project_name "riscv-z710-v2020" -# set variables -set project_dir riscv-z710 -set project_name riscv-z710 -set part xc7z010clg400-1 -set sources {../../verilog/z710/Top.v ../../verilog/z710/clock_control.v ../../verilog/z710/pass_through.v ../../verilog/z710/Top_reset.v ../../verilog/z710/uart_control.v} -set test_sources {../../verilog/z710/test.v ../../verilog/z710/top_test.v} -# open the project. will create one if it doesn't exist -if {[file exist $project_dir]} { - # check that it's a directory - if {! [file isdirectory $project_dir]} { - puts "$project_dir exists, but it's a file" - } - open_project $project_dir/$project_name.xpr -part $part -} else { - source riscv-z710.tcl -} \ No newline at end of file +open_project $project_dir/$project_name.xpr + diff --git a/lab3/vivado/z710/program_device.tcl b/lab3/vivado/z710/program_device.tcl deleted file mode 100644 index dc784fe..0000000 --- a/lab3/vivado/z710/program_device.tcl +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright 2021 Howard Lau -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# Only tested on Vivado 2020.1 on Windows 10 -open_hw_manager -connect_hw_server -allow_non_jtag -open_hw_target -current_hw_device [get_hw_devices xc7z010_1] -refresh_hw_server [current_hw_server] -open_hw_target [lindex [get_hw_targets] 0] -set_property PROGRAM.FILE {./riscv-z710/riscv-z710.runs/impl_1/Top.bit} [get_hw_devices xc7z010_1] -program_hw_devices [get_hw_devices xc7z010_1] -close_hw_target diff --git a/lab3/vivado/z710/riscv-z710-v2020.tcl b/lab3/vivado/z710/riscv-z710-v2020.tcl new file mode 100644 index 0000000..0034547 --- /dev/null +++ b/lab3/vivado/z710/riscv-z710-v2020.tcl @@ -0,0 +1,1170 @@ +#***************************************************************************************** +# Vivado (TM) v2020.1 (64-bit) +# +# riscv-z710-v2020.tcl: Tcl script for re-creating project 'riscv-z710-v2020' +# +# Generated by Vivado on Mon Dec 25 11:27:52 +0800 2023 +# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (riscv-z710-v2020.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# +# +# 3. The following remote source files that were added to the original project:- +# +# "E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v" +# "E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v" +# "E:/Workplace/2022-fall-yatcpu-repo/lab1/vivado/z710/pre-generate-files/v2020/design_1/hdl/design_1_wrapper.v" +# "E:/Workplace/2022-fall-yatcpu-repo/lab1/vivado/z710/z710.xdc" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "riscv-z710-v2020" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "riscv-z710-v2020.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/riscv-z710-v2020"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z010clg400-1 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "digilentinc.com:zybo-z7-10:part0:1.2" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "platform.board_id" -value "zybo-z7-10" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../../verilog/z710/Top.v"] \ + [file normalize "${origin_dir}/../../verilog/z710/clock_control.v"] \ +] +# [file normalize "${origin_dir}/pre-generate-files/v2020/design_1/hdl/design_1_wrapper.v"] \ +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "design_1_wrapper" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/z710.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/z710.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Empty (no sources present) + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj +set_property -name "top" -value "Top" -objects $obj +set_property -name "top_file" -value "../../verilog/z710/Top.v" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + + +# Adding sources referenced in BDs, if not already added +if { [get_files Top.v] == "" } { + import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v +} +if { [get_files clock_control.v] == "" } { + import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v +} + + +# Proc to create BD design_1 +proc cr_bd_design_1 { parentCell } { +# The design that will be created by this Tcl proc contains the following +# module references: +# Top, clock_control + + + + # CHANGE DESIGN NAME HERE + set design_name design_1 + + common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:processing_system7:5.5\ + xilinx.com:ip:xlconstant:1.1\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + ################################################################## + # CHECK Modules + ################################################################## + set bCheckModules 1 + if { $bCheckModules == 1 } { + set list_check_mods "\ + Top\ + clock_control\ + " + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + + + # Create ports + set enable_clk [ create_bd_port -dir I -type data enable_clk ] + set io_alive_led [ create_bd_port -dir O io_alive_led ] + set io_clock [ create_bd_port -dir I -type clk -freq_hz 50000000 io_clock ] + set io_reset [ create_bd_port -dir I -type rst io_reset ] + + # Create instance: Top_0, and set properties + set block_name Top + set block_cell_name Top_0 + if { [catch {set Top_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $Top_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: clock_control_0, and set properties + set block_name clock_control + set block_cell_name clock_control_0 + if { [catch {set clock_control_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $clock_control_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ + CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_CLK0_FREQ {50000000} \ + CONFIG.PCW_CLK1_FREQ {10000000} \ + CONFIG.PCW_CLK2_FREQ {10000000} \ + CONFIG.PCW_CLK3_FREQ {10000000} \ + CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \ + CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \ + CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ + CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ + CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ + CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ + CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ + CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \ + CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ + CONFIG.PCW_ENET0_ENET0_IO {} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET0_RESET_ENABLE {0} \ + CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ + CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_ENET_RESET_ENABLE {1} \ + CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ + CONFIG.PCW_ENET_RESET_SELECT {} \ + CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {} \ + CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_CD_IO {} \ + CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_SDIO_PERIPHERAL_VALID {0} \ + CONFIG.PCW_SINGLE_QSPI_DATA_MODE {} \ + CONFIG.PCW_USB1_RESET_ENABLE {0} \ + CONFIG.PCW_USB_RESET_ENABLE {1} \ + CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ + CONFIG.PCW_USB_RESET_SELECT {