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fixed the wrong assignment of uart output in lab1 z710 Top module

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PurplePower
2024-11-14 10:14:53 +08:00
parent 948b2e64f8
commit 4c36205a7f
1 changed files with 0 additions and 1 deletions
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lab1/src/main/scala/board/z710/Top.scala
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@@ -42,7 +42,6 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
uart.io.bundle <> dummy.io.bundle uart.io.bundle <> dummy.io.bundle
io.tx := uart.io.txd io.tx := uart.io.txd
uart.io.rxd := io.rx uart.io.rxd := io.rx
io.tx := 0.U
val instruction_rom = Module(new InstructionROM(binaryFilename)) val instruction_rom = Module(new InstructionROM(binaryFilename))
val rom_loader = Module(new ROMLoader(instruction_rom.capacity)) val rom_loader = Module(new ROMLoader(instruction_rom.capacity))