From 4c36205a7f529d9b3320af636e5947d2faefab86 Mon Sep 17 00:00:00 2001
From: PurplePower <60787289+PurplePower@users.noreply.github.com>
Date: Thu, 14 Nov 2024 10:14:53 +0800
Subject: [PATCH] fixed the wrong assignment of uart output in lab1 z710 Top
 module

---
 lab1/src/main/scala/board/z710/Top.scala | 1 -
 1 file changed, 1 deletion(-)

diff --git a/lab1/src/main/scala/board/z710/Top.scala b/lab1/src/main/scala/board/z710/Top.scala
index bcecb92..634180b 100644
--- a/lab1/src/main/scala/board/z710/Top.scala
+++ b/lab1/src/main/scala/board/z710/Top.scala
@@ -42,7 +42,6 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
   uart.io.bundle <> dummy.io.bundle
   io.tx := uart.io.txd
   uart.io.rxd := io.rx
-  io.tx := 0.U
 
   val instruction_rom = Module(new InstructionROM(binaryFilename))
   val rom_loader = Module(new ROMLoader(instruction_rom.capacity))