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board updates and fixes

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- now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala
- updated cmakelists.txt
- added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently
This commit is contained in:
PurplePower
2024-11-18 10:50:45 +08:00
parent 358100ec57
commit 3e3c8ba6c0
18 changed files with 1043 additions and 13 deletions
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2
lab4/csrc/CMakeLists.txt
View File

@@ -5,7 +5,7 @@ project(yatcpu-programs C CXX ASM)
# Setting variables
set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O0 --target=riscv32-unknown-elf -march=rv32i -mabi=ilp32")
set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -O0 --target=riscv32-unknown-elf -march=rv32i -mabi=ilp32")
set(C_PROGRAMS tetris hello fibonacci quicksort paging tetris_mmu)
set(C_PROGRAMS tetris hello fibonacci quicksort paging tetris_mmu say_goodbye)
set(ASM_PROGRAMS mmio sb)
set(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/link.lds)
set(LINKER_FLAGS -T ${LINKER_SCRIPT})

3
lab4/src/test/scala/riscv/TestAnnotations.scala
View File

@@ -48,5 +48,6 @@ object WriteVcdEnabler {
}
object TestAnnotations {
val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
// val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
val annos = Seq(VerilatorBackendAnnotation, WriteVcdAnnotation) // enable VCD write by default
}