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board updates and fixes

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- now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala
- updated cmakelists.txt
- added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently
This commit is contained in:
PurplePower
2024-11-18 10:50:45 +08:00
parent 358100ec57
commit 3e3c8ba6c0
18 changed files with 1043 additions and 13 deletions
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3
lab2/src/test/scala/riscv/TestAnnotations.scala
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@@ -48,5 +48,6 @@ object WriteVcdEnabler {
}
object TestAnnotations {
val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
// val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
val annos = Seq(VerilatorBackendAnnotation, WriteVcdAnnotation) // enable VCD write by default
}