board updates and fixes

- now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala
- updated cmakelists.txt
- added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently

lab1/src/test/scala/riscv/BoardTest.scala

@@ -7,13 +7,13 @@ import chisel3._
 import chisel3.util.{is, switch}
 import chiseltest._
 import org.scalatest.flatspec.AnyFlatSpec
-import board.z710.Top
+import board.{z710, z710v1_3, verilator}
 
 
-class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
-  behavior of "Board simulation"
+class Z710_SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Z710 Board simulation"
   it should "say goodbye " in {
-    test(new Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => 
+    test(new z710.Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => 
       
       for (i <- 1 to 50000) {
         c.clock.step(5)
@@ -23,3 +23,17 @@ class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
   }
 }
 
+class Z710v13_SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Z710v1.3 Board simulation"
+  it should "say goodbye " in {
+    test(new z710v1_3.Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => 
+      
+      for (i <- 1 to 50000) {
+        c.clock.step(5)
+        c.io.rx.poke((i % 2).U) // poke some useless value, since rx not yet used
+      }  
+    }
+  }
+}
+
+

lab1/src/test/scala/riscv/TestAnnotations.scala

@@ -48,5 +48,6 @@ object WriteVcdEnabler {
 }
 
 object TestAnnotations {
-  val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+  // val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+  val annos = Seq(VerilatorBackendAnnotation, WriteVcdAnnotation) // enable VCD write by default
 }