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fixex typo in clock_control.v

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PurplePower
2024-11-18 17:37:50 +08:00
parent eba44fe287
commit 28380be03b
1 changed files with 2 additions and 2 deletions
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4
lab1/verilog/z710v1.3/clock_control.v
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@@ -22,12 +22,12 @@
module clock_control( module clock_control(
input clk_in, input clk_in,
input clk_enalbe, input clk_enable,
output clk_out output clk_out
); );
// original clock // original clock
assign clk_out = clk_in & clk_enalbe; assign clk_out = clk_in & clk_enable;
endmodule endmodule