From 28380be03bed76c7f0e4f59baf1420fcde64a112 Mon Sep 17 00:00:00 2001
From: PurplePower <60787289+PurplePower@users.noreply.github.com>
Date: Mon, 18 Nov 2024 17:37:50 +0800
Subject: [PATCH] fixex typo in clock_control.v

---
 lab1/verilog/z710v1.3/clock_control.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lab1/verilog/z710v1.3/clock_control.v b/lab1/verilog/z710v1.3/clock_control.v
index 39a734a..39762e2 100644
--- a/lab1/verilog/z710v1.3/clock_control.v
+++ b/lab1/verilog/z710v1.3/clock_control.v
@@ -22,12 +22,12 @@
 
 module clock_control(
     input clk_in,
-    input clk_enalbe,
+    input clk_enable,
     output clk_out
     );
     
     
     // original clock
-   assign clk_out = clk_in & clk_enalbe;
+   assign clk_out = clk_in & clk_enable;
     
 endmodule