mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
synced 2026-02-20 20:10:14 +00:00
117 lines
2.8 KiB
Verilog
117 lines
2.8 KiB
Verilog
//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
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//Date : Sun Dec 10 14:11:15 2023
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//Host : Tokisakix running 64-bit major release (build 9200)
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//Command : generate_target design_1_wrapper.bd
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//Design : design_1_wrapper
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//Purpose : IP block netlist
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//--------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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module design_1_wrapper
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(DDR_addr,
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DDR_ba,
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DDR_cas_n,
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DDR_ck_n,
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DDR_ck_p,
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DDR_cke,
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DDR_cs_n,
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DDR_dm,
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DDR_dq,
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DDR_dqs_n,
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DDR_dqs_p,
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DDR_odt,
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DDR_ras_n,
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DDR_reset_n,
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DDR_we_n,
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FIXED_IO_ddr_vrn,
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FIXED_IO_ddr_vrp,
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FIXED_IO_mio,
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FIXED_IO_ps_clk,
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FIXED_IO_ps_porb,
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FIXED_IO_ps_srstb,
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enable_clk,
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io_alive_led,
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io_clock,
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io_reset);
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inout [14:0]DDR_addr;
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inout [2:0]DDR_ba;
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inout DDR_cas_n;
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inout DDR_ck_n;
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inout DDR_ck_p;
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inout DDR_cke;
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inout DDR_cs_n;
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inout [3:0]DDR_dm;
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inout [31:0]DDR_dq;
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inout [3:0]DDR_dqs_n;
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inout [3:0]DDR_dqs_p;
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inout DDR_odt;
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inout DDR_ras_n;
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inout DDR_reset_n;
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inout DDR_we_n;
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inout FIXED_IO_ddr_vrn;
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inout FIXED_IO_ddr_vrp;
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inout [53:0]FIXED_IO_mio;
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inout FIXED_IO_ps_clk;
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inout FIXED_IO_ps_porb;
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inout FIXED_IO_ps_srstb;
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input enable_clk;
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output io_alive_led;
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input io_clock;
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input io_reset;
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wire [14:0]DDR_addr;
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wire [2:0]DDR_ba;
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wire DDR_cas_n;
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wire DDR_ck_n;
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wire DDR_ck_p;
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wire DDR_cke;
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wire DDR_cs_n;
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wire [3:0]DDR_dm;
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wire [31:0]DDR_dq;
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wire [3:0]DDR_dqs_n;
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wire [3:0]DDR_dqs_p;
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wire DDR_odt;
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wire DDR_ras_n;
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wire DDR_reset_n;
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wire DDR_we_n;
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wire FIXED_IO_ddr_vrn;
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wire FIXED_IO_ddr_vrp;
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wire [53:0]FIXED_IO_mio;
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wire FIXED_IO_ps_clk;
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wire FIXED_IO_ps_porb;
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wire FIXED_IO_ps_srstb;
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wire enable_clk;
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wire io_alive_led;
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wire io_clock;
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wire io_reset;
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design_1 design_1_i
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(.DDR_addr(DDR_addr),
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.DDR_ba(DDR_ba),
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.DDR_cas_n(DDR_cas_n),
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.DDR_ck_n(DDR_ck_n),
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.DDR_ck_p(DDR_ck_p),
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.DDR_cke(DDR_cke),
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.DDR_cs_n(DDR_cs_n),
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.DDR_dm(DDR_dm),
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.DDR_dq(DDR_dq),
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.DDR_dqs_n(DDR_dqs_n),
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.DDR_dqs_p(DDR_dqs_p),
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.DDR_odt(DDR_odt),
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.DDR_ras_n(DDR_ras_n),
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.DDR_reset_n(DDR_reset_n),
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.DDR_we_n(DDR_we_n),
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.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
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.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
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.FIXED_IO_mio(FIXED_IO_mio),
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.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
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.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
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.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
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.enable_clk(enable_clk),
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.io_alive_led(io_alive_led),
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.io_clock(io_clock),
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.io_reset(io_reset));
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endmodule
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