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ddb70fa96720c2708f0fc09394cad0a5602dcca3
2025-yatcpu/lab2/verilog
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PurplePower ddb70fa967 Fixing Z710 frequency TNS too large 
- now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl
- Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v
- adds Zynq7000 v1.3 for lab2
2024-11-18 22:30:07 +08:00
..
basys3
init repo
2023-12-11 21:50:22 +08:00
pynq
init repo
2023-12-11 21:50:22 +08:00
verilator
init repo
2023-12-11 21:50:22 +08:00
z710
Deleted useless verilog files
2023-12-26 01:18:54 +08:00
z710v1.3
Fixing Z710 frequency TNS too large
2024-11-18 22:30:07 +08:00