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33 lines
601 B
Verilog
33 lines
601 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/12/01 16:32:40
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// Design Name:
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// Module Name: Top_reset
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Top_reset(
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input reset
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);
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initial begin
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reset = 1;
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#25 reset = 0;
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end
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endmodule
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