mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
synced 2026-02-20 20:10:14 +00:00
101 lines
3.4 KiB
Scala
101 lines
3.4 KiB
Scala
// Copyright 2022 Canbin Huang
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package board.z710
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import chisel3._
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import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
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import chisel3.util.Cat
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import peripheral._
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import riscv.Parameters
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import riscv.core.CPU
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class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
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val io = IO(new Bundle() {
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val tx = Output(Bool())
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val rx = Input(Bool())
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val led = Output(Bool()) // z710 has few LEDs, use one for running indicator
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})
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val mem = Module(new Memory(Parameters.MemorySizeInWords))
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// val hdmi_display = Module(new HDMIDisplay)
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// val display = Module(new CharacterDisplay)
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val timer = Module(new Timer)
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val uart = Module(new Uart(frequency = 32_000000, baudRate = 115200)) // 31M or 32M is good, 33M more error
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val dummy = Module(new Dummy)
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// display.io.bundle <> dummy.io.bundle
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mem.io.bundle <> dummy.io.bundle
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mem.io.debug_read_address := 0.U
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timer.io.bundle <> dummy.io.bundle
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uart.io.bundle <> dummy.io.bundle
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io.tx := uart.io.txd
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uart.io.rxd := io.rx
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val instruction_rom = Module(new InstructionROM(binaryFilename))
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val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
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rom_loader.io.rom_data := instruction_rom.io.data
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rom_loader.io.load_address := Parameters.EntryAddress
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instruction_rom.io.address := rom_loader.io.rom_address
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val CPU_clkdiv = RegInit(UInt(2.W),0.U)
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val CPU_tick = Wire(Bool())
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val CPU_next = Wire(UInt(2.W))
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CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U)
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CPU_tick := CPU_clkdiv === 0.U
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CPU_clkdiv := CPU_next
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withClock(CPU_tick.asClock) {
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val cpu = Module(new CPU)
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cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
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cpu.io.instruction_valid := rom_loader.io.load_finished
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mem.io.instruction_address := cpu.io.instruction_address
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cpu.io.instruction := mem.io.instruction
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cpu.io.debug_read_address := 0.U
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when(!rom_loader.io.load_finished) {
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rom_loader.io.bundle <> mem.io.bundle
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cpu.io.memory_bundle.read_data := 0.U
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}.otherwise {
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rom_loader.io.bundle.read_data := 0.U
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when(cpu.io.device_select === 4.U) {
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cpu.io.memory_bundle <> timer.io.bundle
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}.elsewhen(cpu.io.device_select === 2.U) { // deviceSelect = highest 3 bits of address, thus 0x4000_0000 is mapped to UART
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cpu.io.memory_bundle <> uart.io.bundle
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}.otherwise {
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cpu.io.memory_bundle <> mem.io.bundle
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}
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}
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}
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// LED, blinks every second
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val clock_freq = 40_000_000.U
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val led_count = RegInit(0.U(32.W))
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when (led_count >= clock_freq) {
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led_count := 0.U
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}.otherwise {
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led_count := led_count + 1.U
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}
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io.led := (led_count >= (clock_freq >> 1))
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}
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object VerilogGenerator extends App {
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(new ChiselStage).execute(
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Array("-X", "verilog", "-td", "verilog/z710"),
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Seq(ChiselGeneratorAnnotation(() => new Top("say_goodbye.asmbin"))) // program to run on CPU
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)
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} |