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35 lines
635 B
Verilog
35 lines
635 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2021/12/17 16:31:05
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// Design Name:
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// Module Name: test
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module test();
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reg clock;
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reg reset;
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initial begin
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clock = 0;
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forever #1 clock = ~clock;
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end
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initial begin
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reset = 1;
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#2 reset = 0;
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end
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Top top(clock, reset);
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endmodule |