mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
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71 lines
2.4 KiB
Scala
71 lines
2.4 KiB
Scala
// Copyright 2022 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package board.verilator
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import bus.{AXI4LiteSlave, AXI4LiteSlaveBundle, BusArbiter, BusSwitch}
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import chisel3._
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import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
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import peripheral.DummySlave
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import riscv.Parameters
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import riscv.core.CPU
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class Top extends Module {
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val io = IO(new Bundle {
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val signal_interrupt = Input(Bool())
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val mem_slave = new AXI4LiteSlaveBundle(Parameters.AddrBits, Parameters.DataBits)
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val uart_slave = new AXI4LiteSlaveBundle(Parameters.AddrBits, Parameters.DataBits)
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val cpu_debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
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val cpu_debug_read_data = Output(UInt(Parameters.DataWidth))
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})
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// Memory is controlled in C++ code
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val mem_slave = Module(new AXI4LiteSlave(Parameters.AddrBits, Parameters.DataBits))
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io.mem_slave <> mem_slave.io.bundle
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// UART is controlled in C++ code
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val uart_slave = Module(new AXI4LiteSlave(Parameters.AddrBits, Parameters.DataBits))
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io.uart_slave <> uart_slave.io.bundle
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val cpu = Module(new CPU)
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val dummy = Module(new DummySlave)
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val bus_arbiter = Module(new BusArbiter)
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val bus_switch = Module(new BusSwitch)
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bus_arbiter.io.bus_request(0) := true.B
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bus_switch.io.master <> cpu.io.axi4_channels
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bus_switch.io.address := cpu.io.bus_address
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for (i <- 0 until Parameters.SlaveDeviceCount) {
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bus_switch.io.slaves(i) <> dummy.io.channels
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}
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cpu.io.stall_flag_bus := false.B
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cpu.io.instruction_valid := true.B
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bus_switch.io.slaves(0) <> mem_slave.io.channels
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bus_switch.io.slaves(2) <> uart_slave.io.channels
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cpu.io.interrupt_flag := io.signal_interrupt
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cpu.io.debug_read_address := io.cpu_debug_read_address
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io.cpu_debug_read_data := cpu.io.debug_read_data
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}
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object VerilogGenerator extends App {
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(new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/verilator"), Seq(ChiselGeneratorAnnotation(() =>
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new Top)))
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} |