mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
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33 lines
1.3 KiB
Tcl
33 lines
1.3 KiB
Tcl
# Copyright 2021 Howard Lau
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# Only tested on Vivado 2020.1 on Windows 10
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# set variables
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set project_dir riscv-z710
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set project_name riscv-z710
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set part xc7z010clg400-1
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set sources {../../verilog/z710/Top.v ../../verilog/z710/clock_control.v ../../verilog/z710/pass_through.v ../../verilog/z710/Top_reset.v ../../verilog/z710/uart_control.v}
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set test_sources {../../verilog/z710/test.v ../../verilog/z710/top_test.v}
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# open the project. will create one if it doesn't exist
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if {[file exist $project_dir]} {
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# check that it's a directory
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if {! [file isdirectory $project_dir]} {
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puts "$project_dir exists, but it's a file"
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}
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open_project $project_dir/$project_name.xpr -part $part
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} else {
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source riscv-z710.tcl
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} |