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https://github.com/handsomezhuzhu/2025-yatcpu.git
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ddb70fa967
- now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl - Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v - adds Zynq7000 v1.3 for lab2
64 lines
1.9 KiB
Tcl
64 lines
1.9 KiB
Tcl
# Copyright 2021 Howard Lau
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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source open_project.tcl
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update_module_reference design_1_Top_0_0
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while 1 {
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if { [catch {launch_runs synth_1 -jobs 4 } ] } {
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regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code
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if { [string equal $code "12-978"] } {
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puts "Already generated and up-to-date"
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break
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} elseif { [string equal $code "17-69"] } {
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puts "Out of date, reset runs"
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reset_runs synth_1
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continue
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} else {
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puts "UNKNOWN ERROR!!! $errorInfo"
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exit
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}
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}
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break
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}
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wait_on_run synth_1
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while 1 {
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if { [catch {launch_runs impl_1 -jobs 4 -to_step write_bitstream } ] } {
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regexp {ERROR: \[Vivado (\d+-\d+)]} $errorInfo -> code
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if { [string equal $code "12-978"] } {
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puts "Already generated and up-to-date"
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break
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} elseif { [string equal $code "12-1088"] } {
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puts "Out of date, reset runs"
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reset_runs impl_1
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continue
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} else {
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puts "UNKNOWN ERROR!!! $errorInfo"
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exit
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}
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}
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break
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}
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wait_on_run impl_1
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# export hardware platform to Vitis
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set_property pfm_name {} [get_files -all $project_dir/$project_name.srcs/sources_1/bd/design_1/design_1.bd]
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write_hw_platform -fixed -include_bit -force -file $project_dir/design_1_wrapper.xsa
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