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ddb70fa967
- now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl - Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v - adds Zynq7000 v1.3 for lab2
32 lines
1.2 KiB
Tcl
32 lines
1.2 KiB
Tcl
## This file is for SYSU computer organization courses.
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## used for Zynq7010 fpga revision 1.3 2024/02
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# clock, 50 MHz
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set_property IOSTANDARD LVCMOS33 [get_ports io_clock];
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set_property PACKAGE_PIN U18 [get_ports io_clock];
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create_clock -period 20.000 -name io_clock -waveform {0.000 10.000} -add [get_ports io_clock];
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# LEDs
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set_property IOSTANDARD LVCMOS33 [get_ports io_led];
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set_property PACKAGE_PIN J16 [get_ports io_led]; # PL_LED0
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#set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports io_led_1];
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#set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports io_led_2];
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# switches
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set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports clk_enable]; # PL_SW1
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set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports io_reset]; # PL_SW2
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# do NOT assign reset to ANY BUTTON in Vivado 2020, its Utility Vector Logic Not cause unstable TX output
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# while this isn't present in Vivado 2022
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# UART ports
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# rxd assigned to constant 1
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set_property IOSTANDARD LVCMOS33 [get_ports UART0_TX_0]
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set_property PACKAGE_PIN J15 [get_ports UART0_TX_0]
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set_property IOSTANDARD LVCMOS33 [get_ports UART0_RX_0]
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set_property PACKAGE_PIN T19 [get_ports UART0_RX_0]
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