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https://github.com/handsomezhuzhu/2025-yatcpu.git
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79 lines
2.4 KiB
Scala
79 lines
2.4 KiB
Scala
// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package riscv.core
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import chisel3._
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import chisel3.util._
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import riscv.Parameters
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object Registers extends Enumeration {
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type Register = Value
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val zero,
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ra, sp, gp, tp,
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t0, t1, t2, fp,
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s1,
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a0, a1, a2, a3, a4, a5, a6, a7,
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s2, s3, s4, s5, s6, s7, s8, s9, s10, s11,
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t3, t4, t5, t6 = Value
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}
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class RegisterFile extends Module {
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val io = IO(new Bundle {
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val write_enable = Input(Bool())
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val write_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
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val write_data = Input(UInt(Parameters.DataWidth))
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val read_address1 = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
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val read_address2 = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
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val read_data1 = Output(UInt(Parameters.DataWidth))
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val read_data2 = Output(UInt(Parameters.DataWidth))
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val debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
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val debug_read_data = Output(UInt(Parameters.DataWidth))
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})
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val registers = Reg(Vec(Parameters.PhysicalRegisters, UInt(Parameters.DataWidth)))
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when(!reset.asBool) {
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when(io.write_enable && io.write_address =/= 0.U) {
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registers(io.write_address) := io.write_data
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}
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}
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io.read_data1 := MuxCase(
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registers(io.read_address1),
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IndexedSeq(
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(io.read_address1 === 0.U) -> 0.U,
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(io.read_address1 === io.write_address && io.write_enable) -> io.write_data
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)
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)
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io.read_data2 := MuxCase(
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registers(io.read_address2),
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IndexedSeq(
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(io.read_address2 === 0.U) -> 0.U,
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(io.read_address2 === io.write_address && io.write_enable) -> io.write_data
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)
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)
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io.debug_read_data := MuxCase(
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registers(io.debug_read_address),
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IndexedSeq(
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(io.debug_read_address === 0.U) -> 0.U,
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(io.debug_read_address === io.write_address && io.write_enable) -> io.write_data
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)
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)
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}
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