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https://github.com/handsomezhuzhu/2025-yatcpu.git
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40 lines
1.1 KiB
Scala
40 lines
1.1 KiB
Scala
// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package riscv.core
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import chisel3._
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import riscv.Parameters
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class PipelineRegister(width: Int = Parameters.DataBits, defaultValue: UInt = 0.U) extends Module {
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val io = IO(new Bundle {
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val stall = Input(Bool())
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val flush = Input(Bool())
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val in = Input(UInt(width.W))
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val out = Output(UInt(width.W))
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})
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// Lab3(PipelineRegister)
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val register = RegInit(defaultValue)
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when(io.flush) {
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register := defaultValue
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}.elsewhen(io.stall) {
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}.otherwise {
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register := io.in
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}
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io.out := register
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// Lab3(PipelineRegister) End
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}
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