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https://github.com/handsomezhuzhu/2025-yatcpu.git
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100 lines
4.1 KiB
Scala
100 lines
4.1 KiB
Scala
// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package riscv.core
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import chisel3._
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import chisel3.util._
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import riscv.Parameters
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import riscv.core.threestage.CSRDirectAccessBundle
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object CSRRegister {
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// Refer to Spec. Vol.II Page 8-10
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val MSTATUS = 0x300.U(Parameters.CSRRegisterAddrWidth)
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val MIE = 0x304.U(Parameters.CSRRegisterAddrWidth)
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val MTVEC = 0x305.U(Parameters.CSRRegisterAddrWidth)
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val MSCRATCH = 0x340.U(Parameters.CSRRegisterAddrWidth)
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val MEPC = 0x341.U(Parameters.CSRRegisterAddrWidth)
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val MCAUSE = 0x342.U(Parameters.CSRRegisterAddrWidth)
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val CycleL = 0xc00.U(Parameters.CSRRegisterAddrWidth)
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val CycleH = 0xc80.U(Parameters.CSRRegisterAddrWidth)
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}
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class CSR extends Module {
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val io = IO(new Bundle {
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val reg_read_address_id = Input(UInt(Parameters.CSRRegisterAddrWidth))
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val reg_write_enable_ex = Input(Bool())
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val reg_write_address_ex = Input(UInt(Parameters.CSRRegisterAddrWidth))
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val reg_write_data_ex = Input(UInt(Parameters.DataWidth))
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val id_reg_read_data = Output(UInt(Parameters.DataWidth))
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val clint_access_bundle = Flipped(new CSRDirectAccessBundle)
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})
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val mstatus = RegInit(UInt(Parameters.DataWidth), 0.U)
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val mie = RegInit(UInt(Parameters.DataWidth), 0.U)
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val mtvec = RegInit(UInt(Parameters.DataWidth), 0.U)
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val mscratch = RegInit(UInt(Parameters.DataWidth), 0.U)
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val mepc = RegInit(UInt(Parameters.DataWidth), 0.U)
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val mcause = RegInit(UInt(Parameters.DataWidth), 0.U)
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val cycles = RegInit(UInt(64.W), 0.U)
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val regLUT =
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IndexedSeq(
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CSRRegister.MSTATUS -> mstatus,
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CSRRegister.MIE -> mie,
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CSRRegister.MTVEC -> mtvec,
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CSRRegister.MSCRATCH -> mscratch,
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CSRRegister.MEPC -> mepc,
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CSRRegister.MCAUSE -> mcause,
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CSRRegister.CycleL -> cycles(31, 0),
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CSRRegister.CycleH -> cycles(63, 32),
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)
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cycles := cycles + 1.U
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// If the pipeline and the CLINT are going to read and write the CSR at the same time, let the pipeline write first.
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// This is implemented in a single cycle by passing reg_write_data_ex to clint and writing the data from the CLINT to the CSR.
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io.id_reg_read_data := MuxLookup(io.reg_read_address_id, 0.U, regLUT)
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io.clint_access_bundle.mstatus := Mux(io.reg_write_enable_ex && io.reg_write_address_ex === CSRRegister.MSTATUS, io.reg_write_data_ex, mstatus)
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io.clint_access_bundle.mtvec := Mux(io.reg_write_enable_ex && io.reg_write_address_ex === CSRRegister.MTVEC, io.reg_write_data_ex, mtvec)
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io.clint_access_bundle.mcause := Mux(io.reg_write_enable_ex && io.reg_write_address_ex === CSRRegister.MCAUSE, io.reg_write_data_ex, mcause)
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io.clint_access_bundle.mepc := Mux(io.reg_write_enable_ex && io.reg_write_address_ex === CSRRegister.MEPC, io.reg_write_data_ex, mepc)
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when(io.clint_access_bundle.direct_write_enable) {
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mstatus := io.clint_access_bundle.mstatus_write_data
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mepc := io.clint_access_bundle.mepc_write_data
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mcause := io.clint_access_bundle.mcause_write_data
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}.elsewhen(io.reg_write_enable_ex) {
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when(io.reg_write_address_ex === CSRRegister.MSTATUS) {
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mstatus := io.reg_write_data_ex
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}.elsewhen(io.reg_write_address_ex === CSRRegister.MEPC) {
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mepc := io.reg_write_data_ex
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}.elsewhen(io.reg_write_address_ex === CSRRegister.MCAUSE) {
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mcause := io.reg_write_data_ex
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}
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}
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when(io.reg_write_enable_ex) {
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when(io.reg_write_address_ex === CSRRegister.MIE) {
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mie := io.reg_write_data_ex
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}.elsewhen(io.reg_write_address_ex === CSRRegister.MTVEC) {
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mtvec := io.reg_write_data_ex
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}.elsewhen(io.reg_write_address_ex === CSRRegister.MSCRATCH) {
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mscratch := io.reg_write_data_ex
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}
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}
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}
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