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https://github.com/handsomezhuzhu/2025-yatcpu.git
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41 lines
1.4 KiB
Scala
41 lines
1.4 KiB
Scala
// Copyright 2022 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package riscv.core
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import chisel3._
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import riscv.ImplementationType
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import riscv.core.fivestage_final.{CPU => FiveStageCPUFinal}
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import riscv.core.fivestage_forward.{CPU => FiveStageCPUForward}
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import riscv.core.fivestage_stall.{CPU => FiveStageCPUStall}
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import riscv.core.threestage.{CPU => ThreeStageCPU}
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class CPU(val implementation: Int = ImplementationType.FiveStageFinal) extends Module {
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val io = IO(new CPUBundle)
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implementation match {
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case ImplementationType.ThreeStage =>
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val cpu = Module(new ThreeStageCPU)
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cpu.io <> io
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case ImplementationType.FiveStageStall =>
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val cpu = Module(new FiveStageCPUStall)
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cpu.io <> io
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case ImplementationType.FiveStageForward =>
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val cpu = Module(new FiveStageCPUForward)
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cpu.io <> io
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case _ =>
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val cpu = Module(new FiveStageCPUFinal)
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cpu.io <> io
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}
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}
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