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ddb70fa967
- now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl - Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v - adds Zynq7000 v1.3 for lab2
48 lines
995 B
Verilog
48 lines
995 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/12/01 15:46:54
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// Design Name:
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// Module Name: top_test
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module top_test(
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);
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reg clock;
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reg reset;
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reg constant_zero = 1'b0;
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wire io_led, io_tx;
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localparam CLK_PERIOD = 10;
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initial begin
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clock = 1'b0;
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forever #( CLK_PERIOD / 2 ) clock = ~clock;
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end
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initial begin
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reset = 1; // need a down edge to init all components
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#(CLK_PERIOD) reset = 0; // NOTE!!: must happen together with clock down edge!
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end
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Top mytop(clock, reset, io_tx, constant_zero, io_led );
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endmodule
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