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ddb70fa967
- now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl - Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v - adds Zynq7000 v1.3 for lab2
34 lines
652 B
Verilog
34 lines
652 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/11/29 15:52:55
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// Design Name:
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// Module Name: clock_control
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module clock_control(
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input clk_in,
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input clk_enable,
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output clk_out
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);
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// original clock
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assign clk_out = clk_in & clk_enable;
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endmodule
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