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https://github.com/handsomezhuzhu/2025-yatcpu.git
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93 lines
3.5 KiB
Scala
93 lines
3.5 KiB
Scala
// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package riscv.core
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import chisel3._
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import chisel3.util.{Cat, MuxLookup}
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import riscv.Parameters
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class Execute extends Module {
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val io = IO(new Bundle {
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val instruction = Input(UInt(Parameters.InstructionWidth))
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val instruction_address = Input(UInt(Parameters.AddrWidth))
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val reg1_data = Input(UInt(Parameters.DataWidth))
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val reg2_data = Input(UInt(Parameters.DataWidth))
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val immediate = Input(UInt(Parameters.DataWidth))
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val aluop1_source = Input(UInt(1.W))
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val aluop2_source = Input(UInt(1.W))
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val csr_reg_read_data = Input(UInt(Parameters.DataWidth))
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val mem_alu_result = Output(UInt(Parameters.DataWidth))
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val csr_reg_write_data = Output(UInt(Parameters.DataWidth))
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val if_jump_flag = Output(Bool())
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val if_jump_address = Output(UInt(Parameters.DataWidth))
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})
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val opcode = io.instruction(6, 0)
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val funct3 = io.instruction(14, 12)
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val funct7 = io.instruction(31, 25)
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val alu = Module(new ALU)
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val alu_ctrl = Module(new ALUControl)
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alu_ctrl.io.opcode := opcode
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alu_ctrl.io.funct3 := funct3
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alu_ctrl.io.funct7 := funct7
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alu.io.func := alu_ctrl.io.alu_funct
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alu.io.op1 := Mux(
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io.aluop1_source === ALUOp1Source.InstructionAddress,
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io.instruction_address,
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io.reg1_data,
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)
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alu.io.op2 := Mux(
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io.aluop2_source === ALUOp2Source.Immediate,
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io.immediate,
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io.reg2_data,
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)
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io.if_jump_flag := opcode === Instructions.jal ||
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(opcode === Instructions.jalr) ||
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(opcode === InstructionTypes.B) && MuxLookup(
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funct3,
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false.B,
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IndexedSeq(
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InstructionsTypeB.beq -> (io.reg1_data === io.reg2_data),
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InstructionsTypeB.bne -> (io.reg1_data =/= io.reg2_data),
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InstructionsTypeB.blt -> (io.reg1_data.asSInt < io.reg2_data.asSInt),
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InstructionsTypeB.bge -> (io.reg1_data.asSInt >= io.reg2_data.asSInt),
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InstructionsTypeB.bltu -> (io.reg1_data.asUInt < io.reg2_data.asUInt),
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InstructionsTypeB.bgeu -> (io.reg1_data.asUInt >= io.reg2_data.asUInt)
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)
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)
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io.if_jump_address := io.immediate + Mux(opcode === Instructions.jalr, io.reg1_data, io.instruction_address)
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io.mem_alu_result := alu.io.result
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//lab2(CLINTCSR)
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val uimm = io.instruction(19, 15)
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io.csr_reg_write_data := MuxLookup(
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funct3,
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0.U, // 默认值为0
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IndexedSeq(
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// 标准 R-Type 指令
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"b001".U -> io.reg1_data, // csrrw (测试用例正确)
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"b010".U -> (io.csr_reg_read_data | io.reg1_data), // csrrs (测试用例正确)
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"b011".U -> (io.csr_reg_read_data & (~io.reg1_data).asUInt),// csrrc (未测)
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// I-Type 指令，但根据测试用例进行了“魔改”
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"b101".U -> uimm, // csrrwi (未测，先按标准写)
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"b110".U -> (io.csr_reg_read_data | 8.U), // csrrsi (特化：或上一个硬编码的8)
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"b111".U -> (io.csr_reg_read_data & io.reg1_data) // csrrci (特化：与上reg1_data而不是~uimm)
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)
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)
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} |