mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
synced 2026-02-20 20:10:14 +00:00
97 lines
4.0 KiB
Scala
97 lines
4.0 KiB
Scala
// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package riscv.core
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import chisel3._
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import chisel3.util.Cat
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import riscv.{CPUBundle, Parameters}
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class CPU extends Module {
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val io = IO(new CPUBundle)
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val regs = Module(new RegisterFile)
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val inst_fetch = Module(new InstructionFetch)
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val id = Module(new InstructionDecode)
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val ex = Module(new Execute)
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val mem = Module(new MemoryAccess)
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val wb = Module(new WriteBack)
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val csr_regs = Module(new CSR)
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val clint = Module(new CLINT)
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io.regs_debug_read_data := regs.io.debug_read_data
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io.csr_regs_debug_read_data := csr_regs.io.debug_reg_read_data
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regs.io.debug_read_address := io.regs_debug_read_address
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csr_regs.io.debug_reg_read_address := io.csr_regs_debug_read_address
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io.deviceSelect := mem.io.memory_bundle.address(Parameters.AddrBits - 1, Parameters.AddrBits - Parameters.SlaveDeviceCountBits)
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inst_fetch.io.jump_address_id := ex.io.if_jump_address
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inst_fetch.io.jump_flag_id := ex.io.if_jump_flag
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inst_fetch.io.interrupt_assert := clint.io.interrupt_assert
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inst_fetch.io.interrupt_handler_address := clint.io.interrupt_handler_address
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inst_fetch.io.instruction_valid := io.instruction_valid
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inst_fetch.io.instruction_read_data := io.instruction
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io.instruction_address := inst_fetch.io.instruction_address
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regs.io.write_enable := id.io.reg_write_enable
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regs.io.write_address := id.io.reg_write_address
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regs.io.write_data := wb.io.regs_write_data
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regs.io.read_address1 := id.io.regs_reg1_read_address
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regs.io.read_address2 := id.io.regs_reg2_read_address
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id.io.instruction := inst_fetch.io.instruction
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csr_regs.io.clint_access_bundle <> clint.io.csr_bundle
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csr_regs.io.reg_read_address_id := id.io.csr_reg_address
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csr_regs.io.reg_write_data_ex := ex.io.csr_reg_write_data
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csr_regs.io.reg_write_address_id := id.io.csr_reg_address
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csr_regs.io.reg_write_enable_id := id.io.csr_reg_write_enable
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ex.io.instruction := inst_fetch.io.instruction
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ex.io.instruction_address := inst_fetch.io.instruction_address
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ex.io.reg1_data := regs.io.read_data1
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ex.io.reg2_data := regs.io.read_data2
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ex.io.immediate := id.io.ex_immediate
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ex.io.aluop1_source := id.io.ex_aluop1_source
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ex.io.aluop2_source := id.io.ex_aluop2_source
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ex.io.csr_reg_read_data := csr_regs.io.reg_read_data
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mem.io.alu_result := ex.io.mem_alu_result
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mem.io.reg2_data := regs.io.read_data2
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mem.io.memory_read_enable := id.io.memory_read_enable
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mem.io.memory_write_enable := id.io.memory_write_enable
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mem.io.funct3 := inst_fetch.io.instruction(14, 12)
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io.memory_bundle.address := Cat(0.U(Parameters.SlaveDeviceCountBits.W),mem.io.memory_bundle.address(Parameters.AddrBits - 1 - Parameters.SlaveDeviceCountBits, 0))
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io.memory_bundle.write_enable := mem.io.memory_bundle.write_enable
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io.memory_bundle.write_data := mem.io.memory_bundle.write_data
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io.memory_bundle.write_strobe := mem.io.memory_bundle.write_strobe
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mem.io.memory_bundle.read_data := io.memory_bundle.read_data
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wb.io.instruction_address := inst_fetch.io.instruction_address
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wb.io.alu_result := ex.io.mem_alu_result
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wb.io.memory_read_data := mem.io.wb_memory_read_data
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wb.io.regs_write_source := id.io.wb_reg_write_source
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wb.io.csr_read_data := csr_regs.io.reg_read_data
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clint.io.instruction := inst_fetch.io.instruction
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clint.io.instruction_address := inst_fetch.io.instruction_address
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clint.io.interrupt_flag := io.interrupt_flag
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clint.io.jump_flag := ex.io.if_jump_flag
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clint.io.jump_address := ex.io.if_jump_address
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}
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