mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
synced 2026-02-20 20:10:14 +00:00
51 lines
1.6 KiB
Scala
51 lines
1.6 KiB
Scala
// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package peripheral
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import chisel3._
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import riscv.Parameters
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class ROMLoader(capacity: Int) extends Module {
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val io = IO(new Bundle {
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val bundle = Flipped(new RAMBundle)
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val rom_address = Output(UInt(Parameters.AddrWidth))
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val rom_data = Input(UInt(Parameters.InstructionWidth))
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val load_address = Input(UInt(Parameters.AddrWidth))
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val load_finished = Output(Bool())
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})
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val address = RegInit(0.U(32.W))
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val valid = RegInit(false.B)
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io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
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io.bundle.address := 0.U
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io.bundle.write_data := 0.U
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io.bundle.write_enable := false.B
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when(address <= (capacity - 1).U) {
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io.bundle.write_enable := true.B
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io.bundle.write_data := io.rom_data
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io.bundle.address := (address << 2.U).asUInt + io.load_address
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io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(true.B))
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address := address + 1.U
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when(address === (capacity - 1).U) {
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valid := true.B
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}
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}
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io.load_finished := valid
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io.rom_address := address
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}
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