mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
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55 lines
1.3 KiB
Scala
55 lines
1.3 KiB
Scala
// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package board.basys3
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import chisel3._
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import chisel3.util._
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class BCD2Segments extends Module {
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val io = IO(new Bundle {
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val bcd = Input(UInt(4.W))
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val segs = Output(UInt(8.W))
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})
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val bcd = io.bcd
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val segs = Wire(UInt(8.W))
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segs := MuxLookup(
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bcd,
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0xFF.U,
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IndexedSeq(
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0.U -> "b10000001".U,
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1.U -> "b11001111".U,
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2.U -> "b10010010".U,
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3.U -> "b10000110".U,
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4.U -> "b11001100".U,
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5.U -> "b10100100".U,
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6.U -> "b10100000".U,
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7.U -> "b10001111".U,
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8.U -> "b10000000".U,
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9.U -> "b10000100".U,
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10.U -> "b00001000".U,
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11.U -> "b01100000".U,
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12.U -> "b00110001".U,
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13.U -> "b01000010".U,
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14.U -> "b00110000".U,
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15.U -> "b00111000".U,
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)
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)
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io.segs := segs
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}
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