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"duplicate":"~Top|Top/bus_switch:BusSwitch/dummy:DummyMaster/master:AXI4LiteMaster", "index":0.92 }, { "class":"firrtl.transforms.DedupedResult", "original":"~Top|AXI4LiteMaster_2", "duplicate":"~Top|Top/rom_loader:ROMLoader/master:AXI4LiteMaster", "index":0.9733333333333334 }, { "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.AXI4LiteMaster.state", "enumTypeName":"bus.AXI4LiteStates" }, { "class":"firrtl.annotations.MemorySynthInit$" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.AXI4LiteSlave_1.state", "enumTypeName":"bus.AXI4LiteStates" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.AXI4LiteSlave.state", "enumTypeName":"bus.AXI4LiteStates" }, { "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", "typeName":"riscv.core.fivestage.MemoryAccessStates", "definition":{ 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"target":"Top.ALUControl._io_alu_funct_T_25", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_23", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_21", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_17", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_15", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_13", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_11", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_9", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_7", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_5", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_3", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_1", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl.io_alu_funct", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", "typeName":"riscv.core.fivestage.ALUFunctions", "definition":{ "sll":3, "sra":9, "or":6, "xor":5, "slt":4, "sub":2, "add":1, "sltu":10, "and":7, "srl":8, "zero":0 } }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALU.io_func", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", "typeName":"bus.AXI4LiteStates", "definition":{ "ReadData":2, "WriteAddr":3, "WriteResp":5, "Idle":0, "WriteData":4, "ReadAddr":1 } }, { "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", "typeName":"board.z710.BootStates", "definition":{ "Init":0, "Loading":1, "BusWait":2, "Finished":3 } }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.Top.boot_state", "enumTypeName":"board.z710.BootStates" }, { "class":"firrtl.transforms.BlackBoxTargetDirAnno", "targetDir":"verilog/z710" }, { "class":"firrtl.annotations.MemoryFileInlineAnnotation", "target":"~Top|InstructionROM>mem", "filename":"/root/yatcpu/lab4/verilog/say_goodbye.asmbin.txt", "hexOrBinary":"h" } ]