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"duplicate":"~Top|Top/dummy:DummySlave/slave:AXI4LiteSlave_1", "index":0.881578947368421 }, { "class":"firrtl.transforms.DedupedResult", "original":"~Top|AXI4LiteMaster_1", "duplicate":"~Top|Top/bus_switch:BusSwitch/dummy:DummyMaster/master:AXI4LiteMaster", "index":0.9210526315789473 }, { "class":"firrtl.transforms.DedupedResult", "original":"~Top|AXI4LiteMaster_2", "duplicate":"~Top|Top/rom_loader:ROMLoader/master:AXI4LiteMaster", "index":0.9736842105263158 }, { "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.AXI4LiteMaster.state", "enumTypeName":"bus.AXI4LiteStates" }, { "class":"firrtl.annotations.MemorySynthInit$" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.AXI4LiteSlave_1.state", "enumTypeName":"bus.AXI4LiteStates" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.AXI4LiteSlave.state", "enumTypeName":"bus.AXI4LiteStates" }, { "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", "typeName":"riscv.core.fivestage.MEMAccessState", "definition":{ "if_address_translate":1, "if_access":4, "idle":0, "mem_address_translate":2, "mem_access":3 } }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.CPU.mem_access_state", "enumTypeName":"riscv.core.fivestage.MEMAccessState" }, { "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", "typeName":"riscv.core.fivestage.BUSGranted", "definition":{ "mmu_if_granted":4, "if_granted":1, "mmu_mem_granted":3, "mem_granted":2, "idle":0 } }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.CPU.bus_granted", "enumTypeName":"riscv.core.fivestage.BUSGranted" }, { "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", "typeName":"riscv.core.fivestage.MMUStates", "definition":{ "checkpte1":2, "gotPhyicalAddress":6, "setADbit":5, "idle":0, "checkpte0":4, "level1":1, "level0":3 } }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.MMU.state", "enumTypeName":"riscv.core.fivestage.MMUStates" }, { "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", "typeName":"riscv.core.fivestage.MemoryAccessStates", "definition":{ "Idle":0, "Read":1, "Write":2, "ReadWrite":3 } }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.MemoryAccess.mem_access_state", "enumTypeName":"riscv.core.fivestage.MemoryAccessStates" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_33", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_31", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_29", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_27", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_25", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_23", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_21", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_17", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_15", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_13", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_11", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_9", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_7", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_5", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_3", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl._io_alu_funct_T_1", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALUControl.io_alu_funct", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", "typeName":"riscv.core.fivestage.ALUFunctions", "definition":{ "sll":3, "sra":9, "or":6, "xor":5, "slt":4, "sub":2, "add":1, "sltu":10, "and":7, "srl":8, "zero":0 } }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.ALU.io_func", "enumTypeName":"riscv.core.fivestage.ALUFunctions" }, { "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", "typeName":"riscv.core.fivestage.IFAccessStates", "definition":{ "idle":0, "read":1 } }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.InstructionFetch.state", "enumTypeName":"riscv.core.fivestage.IFAccessStates" }, { "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", "typeName":"bus.AXI4LiteStates", "definition":{ "ReadData":2, "WriteAddr":3, "WriteResp":5, "Idle":0, "WriteData":4, "ReadAddr":1 } }, { "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", "typeName":"board.z710.BootStates", "definition":{ "Init":0, "Loading":1, "BusWait":2, "Finished":3 } }, { "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", "target":"Top.Top.boot_state", "enumTypeName":"board.z710.BootStates" }, { "class":"firrtl.transforms.BlackBoxTargetDirAnno", "targetDir":"verilog/z710" }, { "class":"firrtl.annotations.MemoryFileInlineAnnotation", "target":"~Top|InstructionROM>mem", "filename":"/workspaces/2023-fall-yatcpu-repo/mini-yatcpu/verilog/say_goodbye.asmbin.txt", "hexOrBinary":"h" } ]