Commit Graph

10 Commits

Author SHA1 Message Date
PurplePower
b9865cd612 Lab3 pipelined CPU renewed
- added tutorial
- fix ID reg addr invalid in certain types of instructions
- renamed some variables for better understanding
2025-08-14 16:55:53 +08:00
PurplePower
5c930b046c update clock_contrl.v for lab4 Z710 2024-11-19 01:29:05 +08:00
PurplePower
e4a4c6bf20 update clock_control.v for lab4 Z710 2024-11-19 01:17:53 +08:00
PurplePower
8a3fae13fd updates 2024-11-19 00:25:58 +08:00
PurplePower
844cb062c2 Deleted useless verilog files 2023-12-26 01:18:54 +08:00
PurplePower
816f894007 added vivado-vitis uart workflow to lab4
not yet tested
2023-12-26 00:58:59 +08:00
TOKISAKIX\21168
cda1a478ed finished lab4 2023-12-11 23:44:26 +08:00
TOKISAKIX\21168
cfa7e2d2ab update lab4 2023-12-11 23:21:26 +08:00
TOKISAKIX\21168
606393b3b7 add lab4-file 2023-12-11 22:49:10 +08:00
TOKISAKIX\21168
910ee11168 init repo 2023-12-11 21:50:22 +08:00