Commit Graph

8 Commits

Author SHA1 Message Date
PurplePower
bd3a38a3c1 fixes for lab3, passed verilator sim and all tests with correct cf prints 2025-08-15 00:57:34 +08:00
PurplePower
b9865cd612 Lab3 pipelined CPU renewed
- added tutorial
- fix ID reg addr invalid in certain types of instructions
- renamed some variables for better understanding
2025-08-14 16:55:53 +08:00
PurplePower
8a3fae13fd updates 2024-11-19 00:25:58 +08:00
PurplePower
542c34ed46 updates Z7-10 for lab3 and lab4 2024-11-18 23:45:05 +08:00
PurplePower
844cb062c2 Deleted useless verilog files 2023-12-26 01:18:54 +08:00
PurplePower
5ecb75157a added vivado-vitis uart workflow to lab3 2023-12-25 23:40:26 +08:00
TOKISAKIX\21168
90452baed2 add lab3 file 2023-12-12 22:24:33 +08:00
TOKISAKIX\21168
910ee11168 init repo 2023-12-11 21:50:22 +08:00