PurplePower
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b9865cd612
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Lab3 pipelined CPU renewed
- added tutorial
- fix ID reg addr invalid in certain types of instructions
- renamed some variables for better understanding
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2025-08-14 16:55:53 +08:00 |
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PurplePower
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5c930b046c
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update clock_contrl.v for lab4 Z710
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2024-11-19 01:29:05 +08:00 |
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PurplePower
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e4a4c6bf20
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update clock_control.v for lab4 Z710
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2024-11-19 01:17:53 +08:00 |
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PurplePower
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8a3fae13fd
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updates
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2024-11-19 00:25:58 +08:00 |
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PurplePower
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844cb062c2
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Deleted useless verilog files
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2023-12-26 01:18:54 +08:00 |
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PurplePower
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816f894007
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added vivado-vitis uart workflow to lab4
not yet tested
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2023-12-26 00:58:59 +08:00 |
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TOKISAKIX\21168
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cda1a478ed
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finished lab4
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2023-12-11 23:44:26 +08:00 |
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TOKISAKIX\21168
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cfa7e2d2ab
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update lab4
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2023-12-11 23:21:26 +08:00 |
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TOKISAKIX\21168
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606393b3b7
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add lab4-file
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2023-12-11 22:49:10 +08:00 |
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TOKISAKIX\21168
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910ee11168
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init repo
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2023-12-11 21:50:22 +08:00 |
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