5 Commits

Author	SHA1	Message	Date
PurplePower	b9865cd612	Lab3 pipelined CPU renewed ... - added tutorial - fix ID reg addr invalid in certain types of instructions - renamed some variables for better understanding	2025-08-14 16:55:53 +08:00
PurplePower	8a3fae13fd	updates	2024-11-19 00:25:58 +08:00
PurplePower	3e3c8ba6c0	board updates and fixes ... - now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala - updated cmakelists.txt - added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently	2024-11-18 10:50:45 +08:00
TOKISAKIX\21168	2bce97ff4e	add file	2023-12-11 22:20:48 +08:00
TOKISAKIX\21168	910ee11168	init repo	2023-12-11 21:50:22 +08:00