Commit Graph

18 Commits

Author SHA1 Message Date
525360669e lab3截图和小更改 2025-10-14 21:24:47 +08:00
81adb30885 lab3跑完 2025-10-13 18:01:48 +08:00
37ced72a9d lab2实验报告&lab3还有最后一个错误 2025-10-13 16:03:58 +08:00
PurplePower
47c801d5d7 updated anchors and autofiller 2025-08-14 21:57:07 +08:00
PurplePower
c6ff02a058 some updates 2025-08-14 18:19:52 +08:00
PurplePower
b9865cd612 Lab3 pipelined CPU renewed
- added tutorial
- fix ID reg addr invalid in certain types of instructions
- renamed some variables for better understanding
2025-08-14 16:55:53 +08:00
PurplePower
ea09ee5925 updated readmes and better printing 2024-11-19 01:47:50 +08:00
PurplePower
0f87b85f9f update Top.scala for z710v1.3 in lab3 and lab4 2024-11-19 00:50:11 +08:00
PurplePower
8a3fae13fd updates 2024-11-19 00:25:58 +08:00
PurplePower
542c34ed46 updates Z7-10 for lab3 and lab4 2024-11-18 23:45:05 +08:00
PurplePower
0f905afe36 fixes 2024-11-18 23:17:58 +08:00
PurplePower
67896ab727 update csrc for correct UART printing with lower clock frequency 2024-11-18 17:06:23 +08:00
PurplePower
3e3c8ba6c0 board updates and fixes
- now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala
- updated cmakelists.txt
- added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently
2024-11-18 10:50:45 +08:00
PurplePower
2a6899729b Fixed Z7-10 generator duplicate file directory 2023-12-23 00:52:34 +08:00
TOKISAKIX\21168
42bcfd9b9c finished lab3 2023-12-12 23:07:53 +08:00
TOKISAKIX\21168
2bce97ff4e add file 2023-12-11 22:20:48 +08:00
TOKISAKIX\21168
e720a0dfc2 add csrc 2023-12-11 21:54:53 +08:00
TOKISAKIX\21168
910ee11168 init repo 2023-12-11 21:50:22 +08:00