16 Commits

Author	SHA1	Message	Date
PurplePower	b9865cd612	Lab3 pipelined CPU renewed ... - added tutorial - fix ID reg addr invalid in certain types of instructions - renamed some variables for better understanding	2025-08-14 16:55:53 +08:00
PurplePower	3890e3a314	Added auto answer filler and updated anchors for lab2	2025-07-20 15:55:04 +08:00
PurplePower	2caaf3d9f5	[not tested] lab2 codes updated: ... - added environment instruction tests - removed useless classes in CLINT.scala - rename and comments	2025-07-19 21:21:21 +08:00
PurplePower	283eb09fd3	temp fix for lab2 on z710v1.3 board	2024-11-19 02:56:45 +08:00
PurplePower	b4141db235	updates	2024-11-19 02:09:45 +08:00
PurplePower	ea09ee5925	updated readmes and better printing	2024-11-19 01:47:50 +08:00
PurplePower	8a3fae13fd	updates	2024-11-19 00:25:58 +08:00
PurplePower	0f905afe36	fixes	2024-11-18 23:17:58 +08:00
PurplePower	ddb70fa967	Fixing Z710 frequency TNS too large ... - now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl - Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v - adds Zynq7000 v1.3 for lab2	2024-11-18 22:30:07 +08:00
PurplePower	67896ab727	update csrc for correct UART printing with lower clock frequency	2024-11-18 17:06:23 +08:00
PurplePower	3e3c8ba6c0	board updates and fixes ... - now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala - updated cmakelists.txt - added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently	2024-11-18 10:50:45 +08:00
PurplePower	2a6899729b	Fixed Z7-10 generator duplicate file directory	2023-12-23 00:52:34 +08:00
TOKISAKIX\21168	cba231d592	finished lab2	2023-12-12 00:34:29 +08:00
TOKISAKIX\21168	2bce97ff4e	add file	2023-12-11 22:20:48 +08:00
TOKISAKIX\21168	e720a0dfc2	add csrc	2023-12-11 21:54:53 +08:00
TOKISAKIX\21168	910ee11168	init repo	2023-12-11 21:50:22 +08:00